1 /*
2 ** ###################################################################
3 ** Processors: MK82FN256CAx15
4 ** MK82FN256VDC15
5 ** MK82FN256VLL15
6 ** MK82FN256VLQ15
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
15 ** Version: rev. 1.2, 2015-07-29
16 ** Build: b181105
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2018 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2015-04-09)
34 ** Initial version
35 ** - rev. 1.1 (2015-05-28)
36 ** Update according to the reference manual Rev. 0.
37 ** - rev. 1.2 (2015-07-29)
38 ** Correction of backward compatibility.
39 **
40 ** ###################################################################
41 */
42
43 /*!
44 * @file MK82F25615
45 * @version 1.2
46 * @date 2015-07-29
47 * @brief Device specific configuration file for MK82F25615 (implementation file)
48 *
49 * Provides a system configuration function and a global variable that contains
50 * the system frequency. It configures the device and initializes the oscillator
51 * (PLL) that is part of the microcontroller device.
52 */
53
54 #include <stdint.h>
55 #include "fsl_device_registers.h"
56
57
58
59 /* ----------------------------------------------------------------------------
60 -- Core clock
61 ---------------------------------------------------------------------------- */
62
63 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
64
65 /* ----------------------------------------------------------------------------
66 -- SystemInit()
67 ---------------------------------------------------------------------------- */
68
SystemInit(void)69 void SystemInit (void) {
70 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
71 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
72 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
73
74 #if (DISABLE_WDOG)
75 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
76 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
77 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
78 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
79 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
80 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
81 WDOG_STCTRLH_WAITEN_MASK |
82 WDOG_STCTRLH_STOPEN_MASK |
83 WDOG_STCTRLH_ALLOWUPDATE_MASK |
84 WDOG_STCTRLH_CLKSRC_MASK |
85 0x0100U;
86 #endif /* (DISABLE_WDOG) */
87
88 SystemInitHook();
89 }
90
91 /* ----------------------------------------------------------------------------
92 -- SystemCoreClockUpdate()
93 ---------------------------------------------------------------------------- */
94
SystemCoreClockUpdate(void)95 void SystemCoreClockUpdate (void) {
96
97 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
98 uint16_t Divider;
99 uint8_t tmpC7 = 0;
100
101 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
102 /* Output of FLL or PLL is selected */
103 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
104 /* FLL is selected */
105 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
106 /* External reference clock is selected */
107 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
108 case 0x00U:
109 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
110 break;
111 case 0x01U:
112 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
113 break;
114 case 0x02U:
115 default:
116 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
117 break;
118 }
119 tmpC7 = MCG->C7;
120 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
121 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
122 case 0x38U:
123 Divider = 1536U;
124 break;
125 case 0x30U:
126 Divider = 1280U;
127 break;
128 default:
129 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
130 break;
131 }
132 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
133 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
134 }
135 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
136 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
137 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
138 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
139 /* Select correct multiplier to calculate the MCG output clock */
140 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
141 case 0x00U:
142 MCGOUTClock *= 640U;
143 break;
144 case 0x20U:
145 MCGOUTClock *= 1280U;
146 break;
147 case 0x40U:
148 MCGOUTClock *= 1920U;
149 break;
150 case 0x60U:
151 MCGOUTClock *= 2560U;
152 break;
153 case 0x80U:
154 MCGOUTClock *= 732U;
155 break;
156 case 0xA0U:
157 MCGOUTClock *= 1464U;
158 break;
159 case 0xC0U:
160 MCGOUTClock *= 2197U;
161 break;
162 case 0xE0U:
163 MCGOUTClock *= 2929U;
164 break;
165 default:
166 MCGOUTClock *= 640U;
167 break;
168 }
169 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
170 /* PLL is selected */
171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
172 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
173 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
174 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
175 MCGOUTClock /= 2U; /* Calculate the MCG output clock */
176 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
177 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
178 /* Internal reference clock is selected */
179 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
180 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
181 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
182 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
183 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
184 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
185 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
186 /* External reference clock is selected */
187 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
188 case 0x00U:
189 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
190 break;
191 case 0x01U:
192 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
193 break;
194 case 0x02U:
195 default:
196 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
197 break;
198 }
199 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
200 /* Reserved value */
201 return;
202 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
203 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
204 }
205
206 /* ----------------------------------------------------------------------------
207 -- SystemInitHook()
208 ---------------------------------------------------------------------------- */
209
SystemInitHook(void)210 __attribute__ ((weak)) void SystemInitHook (void) {
211 /* Void implementation of the weak function. */
212 }
213
