1 /*
2 ** ###################################################################
3 **     Processors:          MKE16F256VLH16
4 **                          MKE16F256VLL16
5 **                          MKE16F512VLH16
6 **                          MKE16F512VLL16
7 **
8 **     Compilers:           Freescale C/C++ for Embedded ARM
9 **                          GNU C Compiler
10 **                          IAR ANSI C/C++ Compiler for ARM
11 **                          Keil ARM C/C++ Compiler
12 **                          MCUXpresso Compiler
13 **
14 **     Reference manual:    KE1xFP100M168SF0RM, Rev. 2, Aug. 2016
15 **     Version:             rev. 4.0, 2016-09-20
16 **     Build:               b191113
17 **
18 **     Abstract:
19 **         Provides a system configuration function and a global variable that
20 **         contains the system frequency. It configures the device and initializes
21 **         the oscillator (PLL) that is part of the microcontroller device.
22 **
23 **     Copyright 2016 Freescale Semiconductor, Inc.
24 **     Copyright 2016-2019 NXP
25 **     All rights reserved.
26 **
27 **     SPDX-License-Identifier: BSD-3-Clause
28 **
29 **     http:                 www.nxp.com
30 **     mail:                 support@nxp.com
31 **
32 **     Revisions:
33 **     - rev. 1.0 (2015-11-18)
34 **         Initial version.
35 **     - rev. 2.0 (2015-12-03)
36 **         Alpha version based on rev0 RDP.
37 **     - rev. 3.0 (2016-04-13)
38 **         Final version based on rev1 RDP.
39 **     - rev. 4.0 (2016-09-20)
40 **         Updated based on rev2 RDP.
41 **
42 ** ###################################################################
43 */
44 
45 /*!
46  * @file MKE16F16
47  * @version 4.0
48  * @date 2016-09-20
49  * @brief Device specific configuration file for MKE16F16 (implementation file)
50  *
51  * Provides a system configuration function and a global variable that contains
52  * the system frequency. It configures the device and initializes the oscillator
53  * (PLL) that is part of the microcontroller device.
54  */
55 
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58 
59 
60 
61 /* ----------------------------------------------------------------------------
62    -- Core clock
63    ---------------------------------------------------------------------------- */
64 
65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
66 
67 /* ----------------------------------------------------------------------------
68    -- SystemInit()
69    ---------------------------------------------------------------------------- */
70 
SystemInit(void)71 void SystemInit (void) {
72 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
73   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
74 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
75 
76 #if (DISABLE_WDOG)
77   if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U)
78   {
79       WDOG->CNT = WDOG_UPDATE_KEY;
80   }
81   else
82   {
83       WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFF;
84       WDOG->CNT = (WDOG_UPDATE_KEY >> 16) & 0xFFFF;
85   }
86   WDOG->TOVAL = 0xFFFF;
87   WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
88 #endif /* (DISABLE_WDOG) */
89 
90   /* Initialize Cache */
91   /* Enable Code Bus Cache */
92   /* set command to invalidate all ways, enable write buffer
93      and write GO bit to initiate command */
94   LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
95   LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
96   /* Wait until the command completes */
97   while (LMEM->PCCCR & LMEM_PCCCR_GO_MASK) {
98   }
99   /* Enable cache, enable write buffer */
100   LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
101   __ISB();
102 
103   SystemInitHook();
104 }
105 
106 /* ----------------------------------------------------------------------------
107    -- SystemCoreClockUpdate()
108    ---------------------------------------------------------------------------- */
109 
SystemCoreClockUpdate(void)110 void SystemCoreClockUpdate (void) {
111 
112   uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
113   uint16_t Divider, prediv, multi;
114   Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U);
115 
116   switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
117     case 0x1:
118       /* System OSC */
119       SCGOUTClock = CPU_XTAL_CLK_HZ;
120       break;
121     case 0x2:
122       /* Slow IRC */
123       SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U);
124       break;
125     case 0x3:
126       /* Fast IRC */
127       SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
128       break;
129     case 0x6:
130       /* System PLL */
131       if (((SCG->SPLLCFG & SCG_SPLLCFG_SOURCE_MASK) >> SCG_SPLLCFG_SOURCE_SHIFT) != 0U) {
132         SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
133       }
134       else {
135         SCGOUTClock = CPU_XTAL_CLK_HZ;
136       }
137       prediv = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U);
138       multi = (uint16_t)(((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U);
139       SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
140       break;
141     default:
142       return;
143   }
144   SystemCoreClock = (SCGOUTClock / Divider);
145 
146 }
147 
148 /* ----------------------------------------------------------------------------
149    -- SystemInitHook()
150    ---------------------------------------------------------------------------- */
151 
SystemInitHook(void)152 __attribute__ ((weak)) void SystemInitHook (void) {
153   /* Void implementation of the weak function. */
154 }
155