1 /*
2 ** ###################################################################
3 ** Processors: MK80FN256CAx15
4 ** MK80FN256VDC15
5 ** MK80FN256VLL15
6 ** MK80FN256VLQ15
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: K80P121M150SF5RM, Rev. 2, May 2015
15 ** Version: rev. 2.2, 2015-07-29
16 ** Build: b181105
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2018 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2014-07-30)
34 ** Initial version
35 ** - rev. 1.1 (2014-08-28)
36 ** Update of startup files - possibility to override DefaultISR added.
37 ** - rev. 1.2 (2014-11-07)
38 ** Update according to the new version of reference manual Rev. 1 Draft A.
39 ** - rev. 2.0 (2015-04-01)
40 ** Update according to the new version of reference manual Rev. 1.
41 ** - rev. 2.1 (2015-05-28)
42 ** Update according to the reference manual Rev. 2.
43 ** - rev. 2.2 (2015-07-29)
44 ** Correction of backward compatibility.
45 **
46 ** ###################################################################
47 */
48
49 /*!
50 * @file MK80F25615
51 * @version 2.2
52 * @date 2015-07-29
53 * @brief Device specific configuration file for MK80F25615 (implementation file)
54 *
55 * Provides a system configuration function and a global variable that contains
56 * the system frequency. It configures the device and initializes the oscillator
57 * (PLL) that is part of the microcontroller device.
58 */
59
60 #include <stdint.h>
61 #include "fsl_device_registers.h"
62
63
64
65 /* ----------------------------------------------------------------------------
66 -- Core clock
67 ---------------------------------------------------------------------------- */
68
69 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
70
71 /* ----------------------------------------------------------------------------
72 -- SystemInit()
73 ---------------------------------------------------------------------------- */
74
SystemInit(void)75 void SystemInit (void) {
76 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
77 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
78 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
79
80 #if (DISABLE_WDOG)
81 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
82 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
83 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
84 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
85 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
86 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
87 WDOG_STCTRLH_WAITEN_MASK |
88 WDOG_STCTRLH_STOPEN_MASK |
89 WDOG_STCTRLH_ALLOWUPDATE_MASK |
90 WDOG_STCTRLH_CLKSRC_MASK |
91 0x0100U;
92 #endif /* (DISABLE_WDOG) */
93
94 SystemInitHook();
95 }
96
97 /* ----------------------------------------------------------------------------
98 -- SystemCoreClockUpdate()
99 ---------------------------------------------------------------------------- */
100
SystemCoreClockUpdate(void)101 void SystemCoreClockUpdate (void) {
102
103 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
104 uint16_t Divider;
105 uint8_t tmpC7 = 0;
106
107 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
108 /* Output of FLL or PLL is selected */
109 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
110 /* FLL is selected */
111 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
112 /* External reference clock is selected */
113 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
114 case 0x00U:
115 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
116 break;
117 case 0x01U:
118 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
119 break;
120 case 0x02U:
121 default:
122 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
123 break;
124 }
125 tmpC7 = MCG->C7;
126 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
127 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
128 case 0x38U:
129 Divider = 1536U;
130 break;
131 case 0x30U:
132 Divider = 1280U;
133 break;
134 default:
135 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
136 break;
137 }
138 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
139 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
140 }
141 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
142 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
143 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
144 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
145 /* Select correct multiplier to calculate the MCG output clock */
146 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
147 case 0x00U:
148 MCGOUTClock *= 640U;
149 break;
150 case 0x20U:
151 MCGOUTClock *= 1280U;
152 break;
153 case 0x40U:
154 MCGOUTClock *= 1920U;
155 break;
156 case 0x60U:
157 MCGOUTClock *= 2560U;
158 break;
159 case 0x80U:
160 MCGOUTClock *= 732U;
161 break;
162 case 0xA0U:
163 MCGOUTClock *= 1464U;
164 break;
165 case 0xC0U:
166 MCGOUTClock *= 2197U;
167 break;
168 case 0xE0U:
169 MCGOUTClock *= 2929U;
170 break;
171 default:
172 MCGOUTClock *= 640U;
173 break;
174 }
175 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
176 /* PLL is selected */
177 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
178 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
179 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
180 MCGOUTClock *= Divider; /* Calculate the VCO output clock */
181 MCGOUTClock /= 2U; /* Calculate the MCG output clock */
182 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
183 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
184 /* Internal reference clock is selected */
185 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
186 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
187 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
188 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
189 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
190 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
191 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
192 /* External reference clock is selected */
193 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
194 case 0x00U:
195 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
196 break;
197 case 0x01U:
198 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
199 break;
200 case 0x02U:
201 default:
202 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
203 break;
204 }
205 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
206 /* Reserved value */
207 return;
208 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
209 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
210 }
211
212 /* ----------------------------------------------------------------------------
213 -- SystemInitHook()
214 ---------------------------------------------------------------------------- */
215
SystemInitHook(void)216 __attribute__ ((weak)) void SystemInitHook (void) {
217 /* Void implementation of the weak function. */
218 }
219
