Lines Matching refs:Divider
98 uint16_t Divider; in SystemCoreClockUpdate() local
123 Divider = 1536U; in SystemCoreClockUpdate()
126 Divider = 1280U; in SystemCoreClockUpdate()
129 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
133 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
135 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
172 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
173 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
174 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
182 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
183 …MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selecte… in SystemCoreClockUpdate()