1 /*
2 ** ###################################################################
3 **     Processors:          MKW31Z256VHT4
4 **                          MKW31Z512CAT4
5 **                          MKW31Z512VHT4
6 **
7 **     Compilers:           Keil ARM C/C++ Compiler
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
13 **     Version:             rev. 1.0, 2015-09-23
14 **     Build:               b170213
15 **
16 **     Abstract:
17 **         Provides a system configuration function and a global variable that
18 **         contains the system frequency. It configures the device and initializes
19 **         the oscillator (PLL) that is part of the microcontroller device.
20 **
21 **     Copyright 2016 Freescale Semiconductor, Inc.
22 **     Copyright 2016-2017 NXP
23 **     Redistribution and use in source and binary forms, with or without modification,
24 **     are permitted provided that the following conditions are met:
25 **
26 **     o Redistributions of source code must retain the above copyright notice, this list
27 **       of conditions and the following disclaimer.
28 **
29 **     o Redistributions in binary form must reproduce the above copyright notice, this
30 **       list of conditions and the following disclaimer in the documentation and/or
31 **       other materials provided with the distribution.
32 **
33 **     o Neither the name of the copyright holder nor the names of its
34 **       contributors may be used to endorse or promote products derived from this
35 **       software without specific prior written permission.
36 **
37 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
38 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
39 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
40 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
41 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
43 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
44 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
46 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 **
48 **     http:                 www.nxp.com
49 **     mail:                 support@nxp.com
50 **
51 **     Revisions:
52 **     - rev. 1.0 (2015-09-23)
53 **         Initial version.
54 **
55 ** ###################################################################
56 */
57 
58 /*!
59  * @file MKW31Z4
60  * @version 1.0
61  * @date 2015-09-23
62  * @brief Device specific configuration file for MKW31Z4 (implementation file)
63  *
64  * Provides a system configuration function and a global variable that contains
65  * the system frequency. It configures the device and initializes the oscillator
66  * (PLL) that is part of the microcontroller device.
67  */
68 
69 #include <stdint.h>
70 #include "fsl_device_registers.h"
71 
72 
73 
74 /* ----------------------------------------------------------------------------
75    -- Core clock
76    ---------------------------------------------------------------------------- */
77 
78 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
79 
80 /* ----------------------------------------------------------------------------
81    -- SystemInit()
82    ---------------------------------------------------------------------------- */
83 
SystemInit(void)84 void SystemInit (void) {
85 
86 #if (DISABLE_WDOG)
87   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
88   SIM->COPC = (uint32_t)0x00u;
89 #endif /* (DISABLE_WDOG) */
90 
91 }
92 
93 /* ----------------------------------------------------------------------------
94    -- SystemCoreClockUpdate()
95    ---------------------------------------------------------------------------- */
96 
SystemCoreClockUpdate(void)97 void SystemCoreClockUpdate (void) {
98 
99   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
100   uint16_t Divider;
101 
102   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
103     /* FLL is selected */
104     if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
105       /* External reference clock is selected */
106       if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
107         MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
108       } else {
109         MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
110       }
111       if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
112         switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
113         case 0x38U:
114           Divider = 1536U;
115           break;
116         case 0x30U:
117           Divider = 1280U;
118           break;
119         default:
120           Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
121           break;
122         }
123       } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
124         Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
125       }
126       MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
127     } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
128       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
129     } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
130     /* Select correct multiplier to calculate the MCG output clock  */
131     switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
132       case 0x00U:
133         MCGOUTClock *= 640U;
134         break;
135       case 0x20U:
136         MCGOUTClock *= 1280U;
137         break;
138       case 0x40U:
139         MCGOUTClock *= 1920U;
140         break;
141       case 0x60U:
142         MCGOUTClock *= 2560U;
143         break;
144       case 0x80U:
145         MCGOUTClock *= 732U;
146         break;
147       case 0xA0U:
148         MCGOUTClock *= 1464U;
149         break;
150       case 0xC0U:
151         MCGOUTClock *= 2197U;
152         break;
153       case 0xE0U:
154         MCGOUTClock *= 2929U;
155         break;
156       default:
157         break;
158     }
159   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
160     /* Internal reference clock is selected */
161     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
162       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
163     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
164       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
165       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
166     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
167   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
168     /* External reference clock is selected */
169     if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
170       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
171     } else {
172       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
173     }
174   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
175     /* Reserved value */
176     return;
177   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
178   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
179 
180 }
181