| /hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/ |
| D | mss_ethernet_registers.h | 27 #define __IO volatile macro
31 __IO uint32_t NETWORK_CONTROL; /* 0x0000 */
32 __IO uint32_t NETWORK_CONFIG; /* 0x0004 */
34 __IO uint32_t USER_IO; /* 0x000C */
35 __IO uint32_t DMA_CONFIG; /* 0x0010 */
36 __IO uint32_t TRANSMIT_STATUS; /* 0x0014 */
37 __IO uint32_t RECEIVE_Q_PTR; /* 0x0018 */
38 __IO uint32_t TRANSMIT_Q_PTR; /* 0x001C */
39 __IO uint32_t RECEIVE_STATUS; /* 0x0020 */
40 __IO uint32_t INT_STATUS; /* 0x0024 */
[all …]
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| /hal_microchip-latest/mpfs/mpfs_hal/common/nwc/ |
| D | mss_ddr_sgmii_regs.h | 45 __IO uint32_t CFG_MANUAL_ADDRESS_MAP;
48 __IO uint32_t cfg_manual_address_map :1;
54 __IO uint32_t CFG_CHIPADDR_MAP;
57 __IO uint32_t cfg_chipaddr_map :24;
63 __IO uint32_t CFG_CIDADDR_MAP;
66 __IO uint32_t cfg_cidaddr_map :18;
72 __IO uint32_t CFG_MB_AUTOPCH_COL_BIT_POS_LOW;
75 __IO uint32_t cfg_mb_autopch_col_bit_pos_low :3;
81 __IO uint32_t CFG_MB_AUTOPCH_COL_BIT_POS_HIGH;
84 __IO uint32_t cfg_mb_autopch_col_bit_pos_high :4;
[all …]
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| D | mss_ddr_sgmii_phy_defs.h | 32 #ifndef __IO
33 #define __IO volatile macro
229 __IO uint32_t SOFT_RESET_DDR_PHY;
242 __IO uint32_t DDRPHY_MODE;
245 __IO uint32_t DDRMODE :3;
246 __IO uint32_t ECC :1;
247 __IO uint32_t CRC :1;
248 __IO uint32_t Bus_width :3;
249 __IO uint32_t DMI_DBI :1;
250 __IO uint32_t DQ_drive :2;
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| D | mss_scb_nwc_regs.h | 31 #ifndef __IO
32 #define __IO volatile macro
41 __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */
42 __IO uint32_t PLL_CTRL; /*!< Offset: 0x4 */
43 __IO uint32_t PLL_REF_FB; /*!< Offset: 0x8 */
44 __IO uint32_t PLL_FRACN; /*!< Offset: 0xc */
45 __IO uint32_t PLL_DIV_0_1; /*!< Offset: 0x10 */
46 __IO uint32_t PLL_DIV_2_3; /*!< Offset: 0x14 */
47 __IO uint32_t PLL_CTRL2; /*!< Offset: 0x18 */
48 __IO uint32_t PLL_CAL; /*!< Offset: 0x1c */
[all …]
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| D | mss_io_config.h | 84 __IO uint32_t iomux0_cr; /* peripheral is connected to the Fabric or
86 __IO uint32_t iomux1_cr; /* BNK4 SDV PAD 0 to 7 */
87 __IO uint32_t iomux2_cr; /* BNK4 SDV PAD 8 to 13 */
88 __IO uint32_t iomux3_cr; /* BNK2 SDV PAD 14 to 21 */
89 __IO uint32_t iomux4_cr; /* BNK2 SDV PAD 22 to 29 */
90 __IO uint32_t iomux5_cr; /* BNK2 PAD 30 to 37 */
91 __IO uint32_t iomux6_cr; /* MMC/SD Voltage select lines are inverted on
133 __IO uint32_t mssio_bank4_pcode_ncode_vs; /* bank 4- set pcode, ncode and
135 __IO uint32_t mssio_bank2_pcode_ncode_vs; /* bank 2- set pcode, ncode and
143 __IO uint32_t mssio_bank4_io_cfg_0_cr; /* x_vddi Ratio Rx<0-2> == 001
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| D | mss_sgmii.h | 126 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is as…
128 __IO uint32_t dpc_bits; /* DPC Bits Register */
129 __IO uint32_t bank_status; /* Bank Complete Registers */
143 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is as…
145 __IO uint32_t dll_ctrl0; /* DPC Bits Register */
146 __IO uint32_t dll_ctrl1; /* DPC Bits Register */
147 __IO uint32_t dll_stat0; /* DLL control register 0 */
148 __IO uint32_t dll_stat1; /* DLL control register 1 */
149 __IO uint32_t dll_stat2; /* DLL control register 2 */
163 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is a…
[all …]
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| /hal_microchip-latest/mec/ |
| D | MCHP_MEC1701.h | 258 …__IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control …
261 …__IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode …
263 …__IO uint32_t TEST : 1; /*!< [2..2] Test bit …
264 …__IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode …
269 …__IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Regist…
279 …__IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate …
284 …__IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock do…
287 …__IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Cloc…
292 …__IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register …
295 …__IO uint32_t TEST : 8; /*!< [0..7] Test bits …
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| /hal_microchip-latest/mpfs/drivers/mss/mss_can/ |
| D | mss_can.h | 538 __IO uint32_t N_ID:3;
539 __IO uint32_t ID:29;
547 __IO uint32_t DATAHIGH;
548 __IO uint32_t DATALOW;
550 __IO int8_t DATA[8];
557 __IO uint32_t L; /* 32 bit flag */
561 __IO uint32_t NA0:16;
562 __IO uint32_t DLC:4;
563 __IO uint32_t IDE:1;
564 __IO uint32_t RTR:1;
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| /hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/ |
| D | tc_component_fixup_pic32cxsg.h | 352 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
353 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
354 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
355 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
356 …__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle…
357 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set…
358 …__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Statu…
359 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
360 …__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation …
361 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
[all …]
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| D | aes_component_fixup_pic32cxsg.h | 158 __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
159 __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
160 …__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Cle…
161 …__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set…
162 …__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Statu…
163 …__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer …
164 __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
168 __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
171 __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
172 __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
[all …]
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| D | usb_component_fixup_pic32cxsg.h | 780 …__IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK En…
781 …__IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK En…
782 …__IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK En…
783 …__IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK En…
791 …__IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host…
792 …__IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host…
793 …__IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host…
794 …__IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host…
796 …__IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host…
797 …__IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host…
[all …]
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| D | port_component_fixup_pic32cxsg.h | 180 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
181 …__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear…
182 …__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
183 …__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggl…
184 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
185 …__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Cl…
186 …__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Se…
187 …__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value To…
189 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
191 …__IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control …
[all …]
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| D | adc_component_fixup_pic32cxsg.h | 336 __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
337 __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
338 __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
339 __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
340 __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
341 __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
343 __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
344 …__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control …
345 …__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower…
346 …__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper…
[all …]
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| D | rtc_component_fixup_pic32cxsg.h | 836 …__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n …
837 …__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n …
845 __IO RTC_MODE0_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control A */
846 __IO RTC_MODE0_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) MODE0 Control B */
847 …__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) MODE0 Event Control …
848 …__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 16) MODE0 Interrupt Enab…
849 …__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enab…
850 …__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 16) MODE0 Interrupt Flag…
851 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0E (R/W 8) Debug Control */
854 …__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x14 (R/W 8) Frequency Correction…
[all …]
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| D | pdec_component_fixup_pic32cxsg.h | 301 __IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
302 __IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
303 __IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
304 __IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
305 …__IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle…
306 …__IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set…
307 …__IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Statu…
309 __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */
311 __IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
313 __IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */
[all …]
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| D | pm_component_fixup_pic32cxsg.h | 116 __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
117 …__IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration …
119 …__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Cle…
120 …__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set…
121 …__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Statu…
123 …__IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuratio…
124 …__IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configurat…
125 …__IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration…
127 …__IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowl…
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| D | dmac_component_fixup_pic32cxsg.h | 522 …__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Contr…
523 …__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count…
524 …__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Sourc…
525 …__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Desti…
526 …__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Addr…
537 …__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x00 (R/W 32) Channel n Control A …
538 …__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x04 (R/W 8) Channel n Control B …
539 …__IO DMAC_CHPRILVL_Type CHPRILVL; /**< \brief Offset: 0x05 (R/W 8) Channel n Priority L…
540 …__IO DMAC_CHEVCTRL_Type CHEVCTRL; /**< \brief Offset: 0x06 (R/W 8) Channel n Event Cont…
542 …__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x0C (R/W 8) Channel n Interrupt …
[all …]
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| D | eic_component_fixup_pic32cxsg.h | 189 __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
190 …__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interru…
191 …__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interru…
193 __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
194 …__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Cle…
195 …__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set…
196 …__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Statu…
197 …__IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt A…
198 …__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt S…
200 __IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
[all …]
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| D | can_component_fixup_pic32cxsg.h | 1211 …__IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 …
1212 …__IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 …
1213 …__IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element …
1224 …__IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 …
1225 …__IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 …
1226 …__IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element…
1237 …__IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 …
1238 …__IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 …
1239 …__IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element…
1250 …__IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID …
[all …]
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| D | sdhc_component_fixup_pic32cxsg.h | 724 …__IO SDHC_SSAR_Type SSAR; /**< \brief Offset: 0x000 (R/W 32) SDMA System Address…
725 __IO SDHC_BSR_Type BSR; /**< \brief Offset: 0x004 (R/W 16) Block Size */
726 __IO SDHC_BCR_Type BCR; /**< \brief Offset: 0x006 (R/W 16) Block Count */
727 __IO SDHC_ARG1R_Type ARG1R; /**< \brief Offset: 0x008 (R/W 32) Argument 1 */
728 __IO SDHC_TMR_Type TMR; /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */
729 __IO SDHC_CR_Type CR; /**< \brief Offset: 0x00E (R/W 16) Command */
731 __IO SDHC_BDPR_Type BDPR; /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */
733 __IO SDHC_HC1R_Type HC1R; /**< \brief Offset: 0x028 (R/W 8) Host Control 1 */
734 __IO SDHC_PCR_Type PCR; /**< \brief Offset: 0x029 (R/W 8) Power Control */
735 …__IO SDHC_BGCR_Type BGCR; /**< \brief Offset: 0x02A (R/W 8) Block Gap Control */
[all …]
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| /hal_microchip-latest/mpfs/mpfs_hal/common/ |
| D | mss_sysreg.h | 48 #ifndef __IO
49 #define __IO volatile /*!< Defines 'read / write' per macro
3599 __IO uint32_t TEMP0;
3602 __IO uint32_t TEMP1;
3605 __IO uint32_t CLOCK_CONFIG_CR;
3608 __IO uint32_t RTC_CLOCK_CR;
3611 __IO uint32_t FABRIC_RESET_CR;
3614 __IO uint32_t BOOT_FAIL_CR;
3620 __IO uint32_t MSS_RESET_CR;
3623 __IO uint32_t CONFIG_LOCK_CR;
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| D | mss_mpu.h | 82 #ifndef __IO
83 #define __IO volatile macro
94 __IO uint64_t pmp : 38;
95 __IO uint64_t rsrvd : 18;
96 __IO uint64_t mode : 8;
104 __IO uint64_t addr : 38;
105 __IO uint64_t rw : 1;
106 __IO uint64_t id : 4;
107 __IO uint64_t failed : 1;
108 __IO uint64_t padding : (64-44);
[all …]
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| /hal_microchip-latest/pic32c/pic32cxsg/include/pic32cxsg41/component/ |
| D | tc.h | 522 __IO uint32_t TC_CTRLA; /* Offset: 0x00 (R/W 32) Control A */
523 …__IO uint8_t TC_CTRLBCLR; /* Offset: 0x04 (R/W 8) Control B Clear …
524 __IO uint8_t TC_CTRLBSET; /* Offset: 0x05 (R/W 8) Control B Set */
525 …__IO uint16_t TC_EVCTRL; /* Offset: 0x06 (R/W 16) Event Control */
526 …__IO uint8_t TC_INTENCLR; /* Offset: 0x08 (R/W 8) Interrupt Enable…
527 …__IO uint8_t TC_INTENSET; /* Offset: 0x09 (R/W 8) Interrupt Enable…
528 …__IO uint8_t TC_INTFLAG; /* Offset: 0x0A (R/W 8) Interrupt Flag S…
529 __IO uint8_t TC_STATUS; /* Offset: 0x0B (R/W 8) Status */
530 …__IO uint8_t TC_WAVE; /* Offset: 0x0C (R/W 8) Waveform Generat…
531 __IO uint8_t TC_DRVCTRL; /* Offset: 0x0D (R/W 8) Control C */
[all …]
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| /hal_microchip-latest/pic32c/pic32cxsg/include/pic32cxsg61/component/ |
| D | tc.h | 522 __IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
523 …__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clea…
524 …__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set …
525 …__IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control…
526 …__IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enab…
527 …__IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enab…
528 …__IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag…
529 __IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */
530 …__IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Gener…
531 __IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */
[all …]
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| /hal_microchip-latest/pic32c/pic32cxsg/include/pic32cxsg60/component/ |
| D | tc.h | 522 __IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
523 …__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clea…
524 …__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set …
525 …__IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control…
526 …__IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enab…
527 …__IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enab…
528 …__IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag…
529 __IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */
530 …__IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Gener…
531 __IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */
[all …]
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