1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PM_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PM_COMPONENT_FIXUP_H_ 9 10 /* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 15 uint8_t IORET:1; /*!< bit: 2 I/O Retention */ 16 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 17 } bit; /*!< Structure used for bit access */ 18 uint8_t reg; /*!< Type used for register access */ 19 } PM_CTRLA_Type; 20 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 21 22 /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ 23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 24 typedef union { 25 struct { 26 uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */ 27 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 28 } bit; /*!< Structure used for bit access */ 29 uint8_t reg; /*!< Type used for register access */ 30 } PM_SLEEPCFG_Type; 31 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 32 33 /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 34 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 typedef union { 36 struct { 37 uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */ 38 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 39 } bit; /*!< Structure used for bit access */ 40 uint8_t reg; /*!< Type used for register access */ 41 } PM_INTENCLR_Type; 42 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 43 44 /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 45 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 46 typedef union { 47 struct { 48 uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */ 49 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } PM_INTENSET_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 56 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 57 typedef union { // __I to avoid read-modify-write on write-to-clear register 58 struct { 59 __I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */ 60 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 61 } bit; /*!< Structure used for bit access */ 62 uint8_t reg; /*!< Type used for register access */ 63 } PM_INTFLAG_Type; 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */ 71 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 72 uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */ 73 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 74 } bit; /*!< Structure used for bit access */ 75 uint8_t reg; /*!< Type used for register access */ 76 } PM_STDBYCFG_Type; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 /* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */ 80 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 81 typedef union { 82 struct { 83 uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */ 84 uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */ 85 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 86 } bit; /*!< Structure used for bit access */ 87 uint8_t reg; /*!< Type used for register access */ 88 } PM_HIBCFG_Type; 89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 91 /* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */ 92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 93 typedef union { 94 struct { 95 uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */ 96 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 97 } bit; /*!< Structure used for bit access */ 98 uint8_t reg; /*!< Type used for register access */ 99 } PM_BKUPCFG_Type; 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 /* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */ 103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 104 typedef union { 105 struct { 106 uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */ 107 uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */ 108 } bit; /*!< Structure used for bit access */ 109 uint8_t reg; /*!< Type used for register access */ 110 } PM_PWSAKDLY_Type; 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 /** \brief PM hardware registers */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef struct { 116 __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 117 __IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */ 118 RoReg8 Reserved1[0x2]; 119 __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 120 __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 121 __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 122 RoReg8 Reserved2[0x1]; 123 __IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */ 124 __IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */ 125 __IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */ 126 RoReg8 Reserved3[0x7]; 127 __IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */ 128 } Pm; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 132 133 134 #endif /* _MICROCHIP_PIC32CXSG_PM_COMPONENT_FIXUP_H_ */ 135
