Lines Matching refs:__IO
48 #ifndef __IO
49 #define __IO volatile /*!< Defines 'read / write' per macro
3599 __IO uint32_t TEMP0;
3602 __IO uint32_t TEMP1;
3605 __IO uint32_t CLOCK_CONFIG_CR;
3608 __IO uint32_t RTC_CLOCK_CR;
3611 __IO uint32_t FABRIC_RESET_CR;
3614 __IO uint32_t BOOT_FAIL_CR;
3620 __IO uint32_t MSS_RESET_CR;
3623 __IO uint32_t CONFIG_LOCK_CR;
3628 __IO uint32_t RESET_SR;
3632 __IO uint32_t DEVICE_STATUS ;
3645 __IO uint32_t FAB_INTEN_U54_1;
3648 __IO uint32_t FAB_INTEN_U54_2;
3651 __IO uint32_t FAB_INTEN_U54_3;
3654 __IO uint32_t FAB_INTEN_U54_4;
3658 __IO uint32_t FAB_INTEN_MISC;
3673 __IO uint32_t GPIO_INTERRUPT_FAB_CR;
3691 __IO uint32_t APBBUS_CR;
3696 __IO uint32_t SUBBLK_CLOCK_CR;
3700 __IO uint32_t SOFT_RESET_CR;
3705 __IO uint32_t AHBAXI_CR;
3708 __IO uint32_t AHBAPB_CR;
3714 __IO uint32_t DFIAPB_CR;
3717 __IO uint32_t GPIO_CR;
3723 __IO uint32_t MAC0_CR;
3726 __IO uint32_t MAC1_CR;
3729 __IO uint32_t USB_CR;
3732 __IO uint32_t MESH_CR;
3735 __IO uint32_t MESH_SEED_CR;
3738 __IO uint32_t ENVM_CR;
3744 __IO uint32_t QOS_PERIPHERAL_CR;
3747 __IO uint32_t QOS_CPLEXIO_CR;
3750 __IO uint32_t QOS_CPLEXDDR_CR;
3765 __IO uint32_t MPU_VIOLATION_SR;
3768 __IO uint32_t MPU_VIOLATION_INTEN_CR;
3771 __IO uint32_t SW_FAIL_ADDR0_CR;
3774 __IO uint32_t SW_FAIL_ADDR1_CR;
3777 __IO uint32_t EDAC_SR;
3780 __IO uint32_t EDAC_INTEN_CR;
3783 __IO uint32_t EDAC_CNT_MMC;
3786 __IO uint32_t EDAC_CNT_DDRC;
3789 __IO uint32_t EDAC_CNT_MAC0;
3792 __IO uint32_t EDAC_CNT_MAC1;
3795 __IO uint32_t EDAC_CNT_USB;
3798 __IO uint32_t EDAC_CNT_CAN0;
3801 __IO uint32_t EDAC_CNT_CAN1;
3806 __IO uint32_t EDAC_INJECT_CR;
3817 __IO uint32_t MAINTENANCE_INTEN_CR;
3820 __IO uint32_t PLL_STATUS_INTEN_CR;
3823 __IO uint32_t MAINTENANCE_INT_SR;
3826 __IO uint32_t PLL_STATUS_SR;
3829 __IO uint32_t CFM_TIMER_CR;
3835 __IO uint32_t DLL_STATUS_CR;
3838 __IO uint32_t DLL_STATUS_SR;
3846 __IO uint32_t RAM_LIGHTSLEEP_CR;
3850 __IO uint32_t RAM_DEEPSLEEP_CR;
3854 __IO uint32_t RAM_SHUTDOWN_CR;
3858 __IO uint32_t L2_SHUTDOWN_CR;
3898 __IO uint32_t IOMUX0_CR;
3902 __IO uint32_t IOMUX1_CR;
3906 __IO uint32_t IOMUX2_CR;
3910 __IO uint32_t IOMUX3_CR;
3914 __IO uint32_t IOMUX4_CR;
3918 __IO uint32_t IOMUX5_CR;
3922 __IO uint32_t IOMUX6_CR;
3932 __IO uint32_t MSSIO_BANK4_CFG_CR;
3935 __IO uint32_t MSSIO_BANK4_IO_CFG_0_1_CR;
3938 __IO uint32_t MSSIO_BANK4_IO_CFG_2_3_CR;
3941 __IO uint32_t MSSIO_BANK4_IO_CFG_4_5_CR;
3944 __IO uint32_t MSSIO_BANK4_IO_CFG_6_7_CR;
3947 __IO uint32_t MSSIO_BANK4_IO_CFG_8_9_CR;
3950 __IO uint32_t MSSIO_BANK4_IO_CFG_10_11_CR;
3953 __IO uint32_t MSSIO_BANK4_IO_CFG_12_13_CR;
3956 __IO uint32_t MSSIO_BANK2_CFG_CR;
3959 __IO uint32_t MSSIO_BANK2_IO_CFG_0_1_CR;
3962 __IO uint32_t MSSIO_BANK2_IO_CFG_2_3_CR;
3965 __IO uint32_t MSSIO_BANK2_IO_CFG_4_5_CR;
3968 __IO uint32_t MSSIO_BANK2_IO_CFG_6_7_CR;
3971 __IO uint32_t MSSIO_BANK2_IO_CFG_8_9_CR;
3974 __IO uint32_t MSSIO_BANK2_IO_CFG_10_11_CR;
3977 __IO uint32_t MSSIO_BANK2_IO_CFG_12_13_CR;
3980 __IO uint32_t MSSIO_BANK2_IO_CFG_14_15_CR;
3983 __IO uint32_t MSSIO_BANK2_IO_CFG_16_17_CR;
3986 __IO uint32_t MSSIO_BANK2_IO_CFG_18_19_CR;
3989 __IO uint32_t MSSIO_BANK2_IO_CFG_20_21_CR;
3992 __IO uint32_t MSSIO_BANK2_IO_CFG_22_23_CR;
4006 __IO uint32_t MSS_SPARE0_CR;
4009 __IO uint32_t MSS_SPARE1_CR;
4012 __IO uint32_t MSS_SPARE0_SR;
4015 __IO uint32_t MSS_SPARE1_SR;
4018 __IO uint32_t MSS_SPARE2_SR;
4021 __IO uint32_t MSS_SPARE3_SR;
4024 __IO uint32_t MSS_SPARE4_SR;
4027 __IO uint32_t MSS_SPARE5_SR;
4034 __IO uint32_t SPARE_REGISTER_RW;
4037 __IO uint32_t SPARE_REGISTER_W1P;
4043 __IO uint32_t SPARE_PERIM_RW;