1 /*
2  * Copyright (c) 2024 Microchip
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _MICROCHIP_PIC32CXSG_AES_COMPONENT_FIXUP_H_
8 #define _MICROCHIP_PIC32CXSG_AES_COMPONENT_FIXUP_H_
9 
10 /* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
12 typedef union {
13   struct {
14     uint32_t SWRST:1;          /*!< bit:      0  Software Reset                     */
15     uint32_t ENABLE:1;         /*!< bit:      1  Enable                             */
16     uint32_t AESMODE:3;        /*!< bit:  2.. 4  AES Modes of operation             */
17     uint32_t CFBS:3;           /*!< bit:  5.. 7  Cipher Feedback Block Size         */
18     uint32_t KEYSIZE:2;        /*!< bit:  8.. 9  Encryption Key Size                */
19     uint32_t CIPHER:1;         /*!< bit:     10  Cipher Mode                        */
20     uint32_t STARTMODE:1;      /*!< bit:     11  Start Mode Select                  */
21     uint32_t LOD:1;            /*!< bit:     12  Last Output Data Mode              */
22     uint32_t KEYGEN:1;         /*!< bit:     13  Last Key Generation                */
23     uint32_t XORKEY:1;         /*!< bit:     14  XOR Key Operation                  */
24     uint32_t :1;               /*!< bit:     15  Reserved                           */
25     uint32_t CTYPE:4;          /*!< bit: 16..19  Counter Measure Type               */
26     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
27   } bit;                       /*!< Structure used for bit  access                  */
28   uint32_t reg;                /*!< Type      used for register access              */
29 } AES_CTRLA_Type;
30 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
31 
32 /* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
33 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
34 typedef union {
35   struct {
36     uint8_t  START:1;          /*!< bit:      0  Start Encryption/Decryption        */
37     uint8_t  NEWMSG:1;         /*!< bit:      1  New message                        */
38     uint8_t  EOM:1;            /*!< bit:      2  End of message                     */
39     uint8_t  GFMUL:1;          /*!< bit:      3  GF Multiplication                  */
40     uint8_t  :4;               /*!< bit:  4.. 7  Reserved                           */
41   } bit;                       /*!< Structure used for bit  access                  */
42   uint8_t reg;                 /*!< Type      used for register access              */
43 } AES_CTRLB_Type;
44 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
45 
46 /* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
48 typedef union {
49   struct {
50     uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete Interrupt Enable */
51     uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete Interrupt Enable */
52     uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
53   } bit;                       /*!< Structure used for bit  access                  */
54   uint8_t reg;                 /*!< Type      used for register access              */
55 } AES_INTENCLR_Type;
56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
57 
58 /* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
59 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
60 typedef union {
61   struct {
62     uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete Interrupt Enable */
63     uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete Interrupt Enable */
64     uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
65   } bit;                       /*!< Structure used for bit  access                  */
66   uint8_t reg;                 /*!< Type      used for register access              */
67 } AES_INTENSET_Type;
68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
69 
70 /* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
72 typedef union { // __I to avoid read-modify-write on write-to-clear register
73   struct {
74     __I uint8_t  ENCCMP:1;         /*!< bit:      0  Encryption Complete                */
75     __I uint8_t  GFMCMP:1;         /*!< bit:      1  GF Multiplication Complete         */
76     __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
77   } bit;                       /*!< Structure used for bit  access                  */
78   uint8_t reg;                 /*!< Type      used for register access              */
79 } AES_INTFLAG_Type;
80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
81 
82 /* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
83 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
84 typedef union {
85   struct {
86     uint8_t  INDATAPTR:2;      /*!< bit:  0.. 1  Input Data Pointer                 */
87     uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
88   } bit;                       /*!< Structure used for bit  access                  */
89   uint8_t reg;                 /*!< Type      used for register access              */
90 } AES_DATABUFPTR_Type;
91 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
92 
93 /* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
95 typedef union {
96   struct {
97     uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
98     uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
99   } bit;                       /*!< Structure used for bit  access                  */
100   uint8_t reg;                 /*!< Type      used for register access              */
101 } AES_DBGCTRL_Type;
102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
103 
104 /* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
106 typedef union {
107   uint32_t reg;                /*!< Type      used for register access              */
108 } AES_KEYWORD_Type;
109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
110 
111 #endif /* _MICROCHIP_PIC32CXSG_AES_COMPONENT_FIXUP_H_ */
112 
113 /* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
115 typedef union {
116   uint32_t reg;                /*!< Type      used for register access              */
117 } AES_INDATA_Type;
118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
119 
120 /* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
122 typedef union {
123   uint32_t reg;                /*!< Type      used for register access              */
124 } AES_INTVECTV_Type;
125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
126 
127 /* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
129 typedef union {
130   uint32_t reg;                /*!< Type      used for register access              */
131 } AES_HASHKEY_Type;
132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
133 
134 /* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
136 typedef union {
137   uint32_t reg;                /*!< Type      used for register access              */
138 } AES_GHASH_Type;
139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
140 
141 /* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
143 typedef union {
144   uint32_t reg;                /*!< Type      used for register access              */
145 } AES_CIPLEN_Type;
146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
147 
148 /* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
150 typedef union {
151   uint32_t reg;                /*!< Type      used for register access              */
152 } AES_RANDSEED_Type;
153 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
154 
155 /** \brief AES hardware registers */
156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
157 typedef struct {
158   __IO AES_CTRLA_Type            CTRLA;       /**< \brief Offset: 0x00 (R/W 32) Control A */
159   __IO AES_CTRLB_Type            CTRLB;       /**< \brief Offset: 0x04 (R/W  8) Control B */
160   __IO AES_INTENCLR_Type         INTENCLR;    /**< \brief Offset: 0x05 (R/W  8) Interrupt Enable Clear */
161   __IO AES_INTENSET_Type         INTENSET;    /**< \brief Offset: 0x06 (R/W  8) Interrupt Enable Set */
162   __IO AES_INTFLAG_Type          INTFLAG;     /**< \brief Offset: 0x07 (R/W  8) Interrupt Flag Status */
163   __IO AES_DATABUFPTR_Type       DATABUFPTR;  /**< \brief Offset: 0x08 (R/W  8) Data buffer pointer */
164   __IO AES_DBGCTRL_Type          DBGCTRL;     /**< \brief Offset: 0x09 (R/W  8) Debug control */
165        RoReg8                    Reserved1[0x2];
166   __O  AES_KEYWORD_Type          KEYWORD[8];  /**< \brief Offset: 0x0C ( /W 32) Keyword n */
167        RoReg8                    Reserved2[0xC];
168   __IO AES_INDATA_Type           INDATA;      /**< \brief Offset: 0x38 (R/W 32) Indata */
169   __O  AES_INTVECTV_Type         INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
170        RoReg8                    Reserved3[0x10];
171   __IO AES_HASHKEY_Type          HASHKEY[4];  /**< \brief Offset: 0x5C (R/W 32) Hash key n */
172   __IO AES_GHASH_Type            GHASH[4];    /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
173        RoReg8                    Reserved4[0x4];
174   __IO AES_CIPLEN_Type           CIPLEN;      /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
175   __IO AES_RANDSEED_Type         RANDSEED;    /**< \brief Offset: 0x84 (R/W 32) Random Seed */
176 } Aes;
177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
178