1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PORT_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PORT_COMPONENT_FIXUP_H_ 9 10 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ 15 } bit; /*!< Structure used for bit access */ 16 uint32_t reg; /*!< Type used for register access */ 17 } PORT_DIR_Type; 18 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 19 20 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */ 21 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 22 typedef union { 23 struct { 24 uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ 25 } bit; /*!< Structure used for bit access */ 26 uint32_t reg; /*!< Type used for register access */ 27 } PORT_DIRCLR_Type; 28 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 29 30 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */ 31 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 32 typedef union { 33 struct { 34 uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ 35 } bit; /*!< Structure used for bit access */ 36 uint32_t reg; /*!< Type used for register access */ 37 } PORT_DIRSET_Type; 38 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 39 40 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */ 41 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 42 typedef union { 43 struct { 44 uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ 45 } bit; /*!< Structure used for bit access */ 46 uint32_t reg; /*!< Type used for register access */ 47 } PORT_DIRTGL_Type; 48 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 49 50 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */ 51 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 52 typedef union { 53 struct { 54 uint32_t OUT:32; /*!< bit: 0..31 PORT Data Output Value */ 55 } bit; /*!< Structure used for bit access */ 56 uint32_t reg; /*!< Type used for register access */ 57 } PORT_OUT_Type; 58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint32_t OUTCLR:32; /*!< bit: 0..31 PORT Data Output Value Clear */ 65 } bit; /*!< Structure used for bit access */ 66 uint32_t reg; /*!< Type used for register access */ 67 } PORT_OUTCLR_Type; 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */ 71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 typedef union { 73 struct { 74 uint32_t OUTSET:32; /*!< bit: 0..31 PORT Data Output Value Set */ 75 } bit; /*!< Structure used for bit access */ 76 uint32_t reg; /*!< Type used for register access */ 77 } PORT_OUTSET_Type; 78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint32_t OUTTGL:32; /*!< bit: 0..31 PORT Data Output Value Toggle */ 85 } bit; /*!< Structure used for bit access */ 86 uint32_t reg; /*!< Type used for register access */ 87 } PORT_OUTTGL_Type; 88 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 89 90 /* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */ 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 92 typedef union { 93 struct { 94 uint32_t IN:32; /*!< bit: 0..31 PORT Data Input Value */ 95 } bit; /*!< Structure used for bit access */ 96 uint32_t reg; /*!< Type used for register access */ 97 } PORT_IN_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ 105 } bit; /*!< Structure used for bit access */ 106 uint32_t reg; /*!< Type used for register access */ 107 } PORT_CTRL_Type; 108 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 109 110 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */ 111 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 112 typedef union { 113 struct { 114 uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ 115 uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */ 116 uint32_t INEN:1; /*!< bit: 17 Input Enable */ 117 uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ 118 uint32_t :3; /*!< bit: 19..21 Reserved */ 119 uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ 120 uint32_t :1; /*!< bit: 23 Reserved */ 121 uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */ 122 uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */ 123 uint32_t :1; /*!< bit: 29 Reserved */ 124 uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */ 125 uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ 126 } bit; /*!< Structure used for bit access */ 127 uint32_t reg; /*!< Type used for register access */ 128 } PORT_WRCONFIG_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */ 132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 133 typedef union { 134 struct { 135 uint32_t PID0:5; /*!< bit: 0.. 4 PORT Event Pin Identifier 0 */ 136 uint32_t EVACT0:2; /*!< bit: 5.. 6 PORT Event Action 0 */ 137 uint32_t PORTEI0:1; /*!< bit: 7 PORT Event Input Enable 0 */ 138 uint32_t PID1:5; /*!< bit: 8..12 PORT Event Pin Identifier 1 */ 139 uint32_t EVACT1:2; /*!< bit: 13..14 PORT Event Action 1 */ 140 uint32_t PORTEI1:1; /*!< bit: 15 PORT Event Input Enable 1 */ 141 uint32_t PID2:5; /*!< bit: 16..20 PORT Event Pin Identifier 2 */ 142 uint32_t EVACT2:2; /*!< bit: 21..22 PORT Event Action 2 */ 143 uint32_t PORTEI2:1; /*!< bit: 23 PORT Event Input Enable 2 */ 144 uint32_t PID3:5; /*!< bit: 24..28 PORT Event Pin Identifier 3 */ 145 uint32_t EVACT3:2; /*!< bit: 29..30 PORT Event Action 3 */ 146 uint32_t PORTEI3:1; /*!< bit: 31 PORT Event Input Enable 3 */ 147 } bit; /*!< Structure used for bit access */ 148 uint32_t reg; /*!< Type used for register access */ 149 } PORT_EVCTRL_Type; 150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 151 152 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */ 157 uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */ 158 } bit; /*!< Structure used for bit access */ 159 uint8_t reg; /*!< Type used for register access */ 160 } PORT_PMUX_Type; 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */ 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 165 typedef union { 166 struct { 167 uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */ 168 uint8_t INEN:1; /*!< bit: 1 Input Enable */ 169 uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ 170 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 171 uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ 172 uint8_t :1; /*!< bit: 7 Reserved */ 173 } bit; /*!< Structure used for bit access */ 174 uint8_t reg; /*!< Type used for register access */ 175 } PORT_PINCFG_Type; 176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 179 typedef struct { 180 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ 181 __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ 182 __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ 183 __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ 184 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ 185 __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ 186 __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ 187 __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ 188 __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ 189 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ 190 __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ 191 __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */ 192 __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing */ 193 __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration */ 194 __I uint8_t Reserved1[0x20]; 195 } PortGroup; 196 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 197 198 #endif /* _MICROCHIP_PIC32CXSG_PORT_COMPONENT_FIXUP_H_ */ 199
