Lines Matching refs:__IO
258 …__IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control …
261 …__IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode …
263 …__IO uint32_t TEST : 1; /*!< [2..2] Test bit …
264 …__IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode …
269 …__IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Regist…
279 …__IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate …
284 …__IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock do…
287 …__IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Cloc…
292 …__IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register …
295 …__IO uint32_t TEST : 8; /*!< [0..7] Test bits …
296 …__IO uint32_t PLL_LOCK : 1; /*!< [8..8] PLL Lock Status …
301 …__IO uint32_t PCR_PWR_RST_STS; /*!< (@ 0x40080110) PCR Power Reset Status Registe…
310 …__IO uint32_t VBAT_RESET_STATUS: 1; /*!< [5..5] VBAT reset status 0 = No reset occurred …
313 … __IO uint32_t VTR_RESET_STATUS: 1; /*!< [6..6] Indicates the status of VTR_RESET.(R/WC)
316 …__IO uint32_t JTAG_RESET_STATUS: 1; /*!< [7..7] Indicates s RESET_SYS was triggered by a…
328 …__IO uint32_t PWR_RST_CNTRL; /*!< (@ 0x40080114) Power Reset Control Register …
331 …__IO uint32_t PWR_INV : 1; /*!< [0..0] Used by FW to control internal RESET_VCC…
335 …__IO uint32_t HOST_RESET_SELECT: 1; /*!< [8..8] Determines what generates the internal p…
341 …__IO uint32_t SYS_RST; /*!< (@ 0x40080118) System Reset Register …
345 …__IO uint32_t SOFT_SYS_RESET: 1; /*!< [8..8] A write of a 1 forces an assertion of th…
352 …__IO uint32_t SLP_EN_0; /*!< (@ 0x40080130) Sleep Enable 0 Register …
355 …__IO uint32_t JTAG_STAP_SLP_EN: 1; /*!< [0..0] JTAG STAP Enable …
356 …__IO uint32_t EFUSE_SLP_EN: 1; /*!< [1..1] eFuse Enable …
361 …__IO uint32_t SLP_EN_1; /*!< (@ 0x40080134) Sleep Enable 1 Register …
364 …__IO uint32_t INT_SLP_EN : 1; /*!< [0..0] Interrupt Sleep Enable …
365 …__IO uint32_t PECI_SLP_EN: 1; /*!< [1..1] PECI Sleep Enable …
366 …__IO uint32_t TACH0_SLP_EN: 1; /*!< [2..2] TACH0 Sleep Enable (TACH0_SLP_EN) …
368 …__IO uint32_t PWM0_SLP_EN: 1; /*!< [4..4] PWM0 Sleep Enable (PWM0_SLP_EN) …
369 …__IO uint32_t PMC_SLP_EN : 1; /*!< [5..5] PMC Sleep Enable (PMC_SLP_EN) …
370 …__IO uint32_t DMA_SLP_EN : 1; /*!< [6..6] DMA Sleep Enable (DMA_SLP_EN) …
371 …__IO uint32_t TFDP_SLP_EN: 1; /*!< [7..7] TFDP Sleep Enable (TFDP_SLP_EN) …
372 …__IO uint32_t PROCESSOR_SLP_EN: 1; /*!< [8..8] PROCESSOR Sleep Enable (PROCESSOR_SLP_EN…
373 …__IO uint32_t WDT_SLP_EN : 1; /*!< [9..9] WDT Sleep Enable (WDT_SLP_EN) …
374 …__IO uint32_t SMB0_SLP_EN: 1; /*!< [10..10] SMB0 Sleep Enable (SMB0_SLP_EN) …
375 …__IO uint32_t TACH1_SLP_EN: 1; /*!< [11..11] TACH1 Sleep Enable (TACH1_SLP_EN) …
376 …__IO uint32_t TACH2_SLP_EN: 1; /*!< [12..12] TACH2 Sleep Enable (TACH2_SLP_EN) …
378 …__IO uint32_t PWM1_SLP_EN: 1; /*!< [20..20] PWM1 Sleep Enable (PWM1_SLP_EN) …
379 …__IO uint32_t PWM2_SLP_EN: 1; /*!< [21..21] PWM2 Sleep Enable (PWM2_SLP_EN) …
380 …__IO uint32_t PWM3_SLP_EN: 1; /*!< [22..22] PWM3 Sleep Enable (PWM3_SLP_EN) …
381 …__IO uint32_t PWM4_SLP_EN: 1; /*!< [23..23] PWM4 Sleep Enable (PWM4_SLP_EN) …
382 …__IO uint32_t PWM5_SLP_EN: 1; /*!< [24..24] PWM3 Sleep Enable (PWM5_SLP_EN) …
383 …__IO uint32_t PWM6_SLP_EN: 1; /*!< [25..25] PWM3 Sleep Enable (PWM6_SLP_EN) …
384 …__IO uint32_t PWM7_SLP_EN: 1; /*!< [26..26] PWM3 Sleep Enable (PWM7_SLP_EN) …
385 …__IO uint32_t PWM8_SLP_EN: 1; /*!< [27..27] PWM3 Sleep Enable (PWM8_SLP_EN) …
387 …__IO uint32_t EC_REG_BANK_SLP_EN: 1; /*!< [29..29] EC_REG_BANK Sleep Enable (EC_REG_BANK_…
388 …__IO uint32_t TIMER16_0_SLP_EN: 1; /*!< [30..30] TIMER16_0 Sleep Enable (TIMER16_0_SLP_…
389 …__IO uint32_t TIMER16_1_SLP_EN: 1; /*!< [31..31] TIMER16_1 Sleep Enable (TIMER16_1_SLP_…
394 …__IO uint32_t SLP_EN_2; /*!< (@ 0x40080138) Sleep Enable 2 Register …
397 …__IO uint32_t LPC_SLP_EN : 1; /*!< [0..0] LPC Sleep Enable (LPC_SLP_EN) …
398 …__IO uint32_t UART_0_SLP_EN: 1; /*!< [1..1] UART 0 Sleep Enable …
399 …__IO uint32_t UART_1_SLP_EN: 1; /*!< [2..2] UART 1 Sleep Enable …
401 …__IO uint32_t GLBL_CFG_SLP_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_SLP_EN) …
402 …__IO uint32_t ACPI_EC_0_SLP_EN: 1; /*!< [13..13] ACPI EC 0 Sleep Enable (ACPI_EC_0_SLP_…
403 …__IO uint32_t ACPI_EC_1_SLP_EN: 1; /*!< [14..14] ACPI EC 1 Sleep Enable (ACPI_EC_1_SLP_…
404 …__IO uint32_t ACPI_PM1_SLP_EN: 1; /*!< [15..15] ACPI PM1 Sleep Enable (ACPI_PM1_SLP_EN…
405 …__IO uint32_t KBCEM_SLP_EN: 1; /*!< [16..16] 8042EM Sleep Enable (8042EM_SLP_EN) …
406 …__IO uint32_t MBX_SLP_EN : 1; /*!< [17..17] Mailbox Sleep Enable (8042EM_SLP_EN) …
407 …__IO uint32_t RTC_SLP_EN : 1; /*!< [18..18] RTC Sleep Enable (RTC_SLP_EN) …
408 …__IO uint32_t ESPI_SLP_EN: 1; /*!< [19..19] eSPI Sleep Enable …
410 …__IO uint32_t ACPI_EC_2_SLP_EN: 1; /*!< [21..21] ACPI EC 2 Sleep Enable (ACPI_EC_2_SLP_…
411 …__IO uint32_t ACPI_EC_3_SLP_EN: 1; /*!< [22..22] ACPI EC 3 Sleep Enable (ACPI_EC_3_SLP_…
412 …__IO uint32_t ACPI_EC_4_SLP_EN: 1; /*!< [23..23] ACPI EC 4 Sleep Enable (ACPI_EC_4_SLP_…
414 …__IO uint32_t PORT80_0_SLP_EN: 1; /*!< [25..25] Port 80 0 Sleep Enable …
415 …__IO uint32_t PORT80_1_SLP_EN: 1; /*!< [26..26] Port 80 1 Sleep Enable …
420 …__IO uint32_t SLP_EN_3; /*!< (@ 0x4008013C) Sleep Enable 3 Register …
424 …__IO uint32_t ADC_SLP_EN : 1; /*!< [3..3] ADC Sleep Enable (ADC_SLP_EN) …
426 …__IO uint32_t PS2_0_SLP_EN: 1; /*!< [5..5] PS2_0 Sleep Enable (PS2_0_SLP_EN) …
427 …__IO uint32_t PS2_1_SLP_EN: 1; /*!< [6..6] PS2_1 Sleep Enable (PS2_1_SLP_EN) …
428 …__IO uint32_t PS2_2_SLP_EN: 1; /*!< [7..7] PS2_2 Sleep Enable (PS2_2_SLP_EN) …
430 …__IO uint32_t GP_SPI0_SLP_EN: 1; /*!< [9..9] GP SPI0 Sleep Enable (GP_SPI0_SLP_EN) …
431 …__IO uint32_t HTIMER_0_SLP_EN: 1; /*!< [10..10] HTIMER 0 Sleep Enable (HTIMER_0_SLP_EN…
432 …__IO uint32_t KEYSCAN_SLP_EN: 1; /*!< [11..11] KEYSCAN Sleep Enable (KEYSCAN_SLP_EN) …
433 …__IO uint32_t RPMPWM_SLP_EN: 1; /*!< [12..12] RPM-PWM Sleep Enable (RPMPWM_SLP_EN) …
434 …__IO uint32_t SMB1_SLP_EN: 1; /*!< [13..13] SMB1 Sleep Enable (SMB1_SLP_EN) …
435 …__IO uint32_t SMB2_SLP_EN: 1; /*!< [14..14] SMB2 Sleep Enable (SMB2_SLP_EN) …
436 …__IO uint32_t SMB3_SLP_EN: 1; /*!< [15..15] SMB3 Sleep Enable (SMB3_SLP_EN) …
437 …__IO uint32_t LED0_SLP_EN: 1; /*!< [16..16] LED0 Sleep Enable (LED0_SLP_EN) …
438 …__IO uint32_t LED1_SLP_EN: 1; /*!< [17..17] LED1 Sleep Enable (LED1_SLP_EN) …
439 …__IO uint32_t LED2_SLP_EN: 1; /*!< [18..18] LED2 Sleep Enable (LED2_SLP_EN) …
440 …__IO uint32_t BCM0_SLP_EN: 1; /*!< [19..19] BCM 0 Sleep Enable (BCM0_SLP_EN) …
441 …__IO uint32_t GP_SPI1_SLP_EN: 1; /*!< [20..20] GP SPI1 Sleep Enable (GP_SPI1_SLP_EN) …
442 …__IO uint32_t TIMER16_2_SLP_EN: 1; /*!< [21..21] TIMER16_2_Sleep Enable (TIMER16_2_SLP_…
443 …__IO uint32_t TIMER16_3_SLP_EN: 1; /*!< [22..22] TIMER16_3 Sleep Enable (TIMER16_3_SLP_…
444 …__IO uint32_t TIMER32_0_SLP_EN: 1; /*!< [23..23] TIMER32_0 Sleep Enable (TIMER32_0_SLP_…
445 …__IO uint32_t TIMER32_1_SLP_EN: 1; /*!< [24..24] TIMER32_1 Sleep Enable (TIMER32_1_SLP_…
446 …__IO uint32_t LED3_SLP_EN: 1; /*!< [25..25] LED3 Sleep Enable (LED3_SLP_EN) …
447 …__IO uint32_t PKE_SLP_EN : 1; /*!< [26..26] PKE Sleep Enable …
448 …__IO uint32_t RNG_SLP_EN : 1; /*!< [27..27] RNG Sleep Enable …
449 …__IO uint32_t AES_HASH_SLP_EN: 1; /*!< [28..28] AES_HASH Sleep Enable …
450 …__IO uint32_t HTIMER_1_SLP_EN: 1; /*!< [29..29] HTIMER 1 Sleep Enable (HTIMER_1_SLP_EN…
451 …__IO uint32_t CCTIMER_SLP_EN: 1; /*!< [30..30] Capture Compare Timer Sleep Enable (CC…
453 …__IO uint32_t PWM9_SLP_EN: 1; /*!< [31..31] PWM9 Sleep Enable (PWM9_SLP_EN) …
458 …__IO uint32_t SLP_EN_4; /*!< (@ 0x40080140) Sleep Enable 4 Register …
461 …__IO uint32_t PWM10_SLP_EN: 1; /*!< [0..0] PWM10 Sleep Enable (PWM10_SLP_EN) …
462 …__IO uint32_t PWM11_SLP_EN: 1; /*!< [1..1] PWM11 Sleep Enable (PWM11_SLP_EN) …
463 …__IO uint32_t CNT_TMER0_SLP_EN: 1; /*!< [2..2] CNT_TMER0 Sleep Enable (CNT_TMER0_SLP_EN…
464 …__IO uint32_t CNT_TMER1_SLP_EN: 1; /*!< [3..3] CNT_TMER1 Sleep Enable (CNT_TMER1_SLP_EN…
465 …__IO uint32_t CNT_TMER2_SLP_EN: 1; /*!< [4..4] CNT_TMER2 Sleep Enable (CNT_TMER2_SLP_EN…
466 …__IO uint32_t CNT_TMER3_SLP_EN: 1; /*!< [5..5] CNT_TMER3 Sleep Enable (CNT_TMER3_SLP_EN…
467 …__IO uint32_t RTOS_SLP_EN: 1; /*!< [6..6] PWM6 Sleep Enable (RTOS_SLP_EN) …
468 …__IO uint32_t RPMPWM1_SLP_EN: 1; /*!< [7..7] RPMPWM 1 Sleep Enable (RPMPWM1_SLP_EN) …
469 …__IO uint32_t QSPI_SLP_EN: 1; /*!< [8..8] Quad SPI Sleep Enable …
470 …__IO uint32_t BCM1_SLP_EN: 1; /*!< [9..9] BCM 1 Sleep Enable (BCM1_SLP_EN) …
471 …__IO uint32_t RC_ID0_SLP_EN: 1; /*!< [10..10] RC_ID0 Sleep Enable (RC_ID0_SLP_EN) …
472 …__IO uint32_t RC_ID1_SLP_EN: 1; /*!< [11..11] RC_ID1 Sleep Enable (RC_ID1_SLP_EN) …
473 …__IO uint32_t RC_ID2_SLP_EN: 1; /*!< [12..12] RC_ID2 Sleep Enable (RC_ID2_SLP_EN) …
479 …__IO uint32_t CLK_REQ_0; /*!< (@ 0x40080150) Clock Required 0 Register …
482 …__IO uint32_t JTAG_STAP_CLK_REQ: 1; /*!< [0..0] JTAG STAP Enable …
483 …__IO uint32_t EFUSE_CLK_REQ: 1; /*!< [1..1] eFuse Enable …
488 …__IO uint32_t CLK_REQ_1; /*!< (@ 0x40080154) Clock Required 1 Register …
491 …__IO uint32_t INT_CLK_REQ: 1; /*!< [0..0] Interrupt Clock Required …
492 …__IO uint32_t PECI_CLK_REQ: 1; /*!< [1..1] PECI Clock Required …
493 …__IO uint32_t TACH0_CLK_REQ: 1; /*!< [2..2] TACH0 Clock Required (TACH0_CLK_REQ) …
495 …__IO uint32_t PWM0_CLK_REQ: 1; /*!< [4..4] PWM0 Clock Required (PWM0_CLK_REQ) …
496 …__IO uint32_t PMC_CLK_REQ: 1; /*!< [5..5] PMC Clock Required (PMC_CLK_REQ) …
497 …__IO uint32_t DMA_CLK_REQ: 1; /*!< [6..6] DMA Clock Required (DMA_CLK_REQ) …
498 …__IO uint32_t TFDP_CLK_REQ: 1; /*!< [7..7] TFDP Clock Required (TFDP_CLK_REQ) …
499 …__IO uint32_t PROCESSOR_CLK_REQ: 1; /*!< [8..8] PROCESSOR Clock Required (PROCESSOR_CLK_…
500 …__IO uint32_t WDT_CLK_REQ: 1; /*!< [9..9] WDT Clock Required (WDT_CLK_REQ) …
501 …__IO uint32_t SMB0_CLK_REQ: 1; /*!< [10..10] SMB0 Clock Required (SMB0_CLK_REQ) …
502 …__IO uint32_t TACH1_CLK_REQ: 1; /*!< [11..11] TACH1 Clock Required (TACH1_CLK_REQ) …
503 …__IO uint32_t TACH2_CLK_REQ: 1; /*!< [12..12] TACH2 Clock Required (TACH2_CLK_REQ) …
505 …__IO uint32_t PWM1_CLK_REQ: 1; /*!< [20..20] PWM1 Clock Required (PWM1_CLK_REQ) …
506 …__IO uint32_t PWM2_CLK_REQ: 1; /*!< [21..21] PWM2 Clock Required (PWM2_CLK_REQ) …
507 …__IO uint32_t PWM3_CLK_REQ: 1; /*!< [22..22] PWM3 Clock Required (PWM3_CLK_REQ) …
508 …__IO uint32_t PWM4_CLK_REQ: 1; /*!< [23..23] PWM4 Clock Required (PWM4_CLK_REQ) …
509 …__IO uint32_t PWM5_CLK_REQ: 1; /*!< [24..24] PWM3 Clock Required (PWM5_CLK_REQ) …
510 …__IO uint32_t PWM6_CLK_REQ: 1; /*!< [25..25] PWM3 Clock Required (PWM6_CLK_REQ) …
511 …__IO uint32_t PWM7_CLK_REQ: 1; /*!< [26..26] PWM3 Clock Required (PWM7_CLK_REQ) …
512 …__IO uint32_t PWM8_CLK_REQ: 1; /*!< [27..27] PWM3 Clock Required (PWM8_CLK_REQ) …
514 …__IO uint32_t EC_REG_BANK_CLK_REQ: 1; /*!< [29..29] EC_REG_BANK Clock Required (EC_REG_BAN…
515 …__IO uint32_t TIMER16_0_CLK_REQ: 1; /*!< [30..30] TIMER16_0 Clock Required (TIMER16_0_CL…
516 …__IO uint32_t TIMER16_1_CLK_REQ: 1; /*!< [31..31] TIMER16_1 Clock Required (TIMER16_1_CL…
521 …__IO uint32_t CLK_REQ_2; /*!< (@ 0x40080158) Clock Required 2 Register …
524 …__IO uint32_t LPC_CLK_REQ: 1; /*!< [0..0] LPC Clock Required (LPC_CLK_REQ) …
525 …__IO uint32_t UART_0_CLK_REQ: 1; /*!< [1..1] UART 0 Clock Required …
526 …__IO uint32_t UART_1_CLK_REQ: 1; /*!< [2..2] UART 1 Clock Required …
528 …__IO uint32_t GLBL_CFG_CLK_REQ: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_CLK_REQ) …
529 …__IO uint32_t ACPI_EC_0_CLK_REQ: 1; /*!< [13..13] ACPI EC 0 Clock Required (ACPI_EC_0_CL…
530 …__IO uint32_t ACPI_EC_1_CLK_REQ: 1; /*!< [14..14] ACPI EC 1 Clock Required (ACPI_EC_1_CL…
531 …__IO uint32_t ACPI_PM1_CLK_REQ: 1; /*!< [15..15] ACPI PM1 Clock Required (ACPI_PM1_CLK_…
532 …__IO uint32_t KBCEM_CLK_REQ: 1; /*!< [16..16] 8042EM Clock Required (8042EM_CLK_REQ)…
533 …__IO uint32_t MBX_CLK_REQ: 1; /*!< [17..17] Mailbox Clock Required (8042EM_CLK_REQ…
534 …__IO uint32_t RTC_CLK_REQ: 1; /*!< [18..18] RTC Clock Required (RTC_CLK_REQ) …
535 …__IO uint32_t ESPI_CLK_REQ: 1; /*!< [19..19] eSPI Clock Required …
537 …__IO uint32_t ACPI_EC_2_CLK_REQ: 1; /*!< [21..21] ACPI EC 2 Clock Required (ACPI_EC_2_CL…
538 …__IO uint32_t ACPI_EC_3_CLK_REQ: 1; /*!< [22..22] ACPI EC 3 Clock Required (ACPI_EC_3_CL…
539 …__IO uint32_t ACPI_EC_4_CLK_REQ: 1; /*!< [23..23] ACPI EC 4 Clock Required (ACPI_EC_4_CL…
541 …__IO uint32_t PORT80_0_CLK_REQ: 1; /*!< [25..25] Port 80 0 Clock Required …
542 …__IO uint32_t PORT80_1_CLK_REQ: 1; /*!< [26..26] Port 80 1 Clock Required …
547 …__IO uint32_t CLK_REQ_3; /*!< (@ 0x4008015C) Clock Required 3 Register …
551 …__IO uint32_t ADC_CLK_REQ: 1; /*!< [3..3] ADC Clock Required (ADC_CLK_REQ) …
553 …__IO uint32_t PS2_0_CLK_REQ: 1; /*!< [5..5] PS2_0 Clock Required (PS2_0_CLK_REQ) …
554 …__IO uint32_t PS2_1_CLK_REQ: 1; /*!< [6..6] PS2_1 Clock Required (PS2_1_CLK_REQ) …
555 …__IO uint32_t PS2_2_CLK_REQ: 1; /*!< [7..7] PS2_2 Clock Required (PS2_2_CLK_REQ) …
557 …__IO uint32_t GP_SPI0_CLK_REQ: 1; /*!< [9..9] GP SPI0 Clock Required (GP_SPI0_CLK_REQ)…
558 …__IO uint32_t HTIMER_0_CLK_REQ: 1; /*!< [10..10] HTIMER 0 Clock Required (HTIMER_0_CLK_…
559 …__IO uint32_t KEYSCAN_CLK_REQ: 1; /*!< [11..11] KEYSCAN Clock Required (KEYSCAN_CLK_RE…
560 …__IO uint32_t RPMPWM0_CLK_REQ: 1; /*!< [12..12] RPM-PWM 0 Clock Required (RPMPWM0_CLK_…
561 …__IO uint32_t SMB1_CLK_REQ: 1; /*!< [13..13] SMB1 Clock Required (SMB1_CLK_REQ) …
562 …__IO uint32_t SMB2_CLK_REQ: 1; /*!< [14..14] SMB2 Clock Required (SMB2_CLK_REQ) …
563 …__IO uint32_t SMB3_CLK_REQ: 1; /*!< [15..15] SMB3 Clock Required (SMB3_CLK_REQ) …
564 …__IO uint32_t LED0_CLK_REQ: 1; /*!< [16..16] LED0 Clock Required (LED0_CLK_REQ) …
565 …__IO uint32_t LED1_CLK_REQ: 1; /*!< [17..17] LED1 Clock Required (LED1_CLK_REQ) …
566 …__IO uint32_t LED2_CLK_REQ: 1; /*!< [18..18] LED2 Clock Required (LED2_CLK_REQ) …
567 …__IO uint32_t BCM0_CLK_REQ: 1; /*!< [19..19] BCM 0 Clock Required (BCM0_CLK_REQ) …
568 …__IO uint32_t GP_SPI1_CLK_REQ: 1; /*!< [20..20] GP SPI1 Clock Required (GP_SPI1_CLK_RE…
569 …__IO uint32_t TIMER16_2_CLK_REQ: 1; /*!< [21..21] TIMER16_2_Clock Required (TIMER16_2_CL…
570 …__IO uint32_t TIMER16_3_CLK_REQ: 1; /*!< [22..22] TIMER16_3 Clock Required (TIMER16_3_CL…
571 …__IO uint32_t TIMER32_0_CLK_REQ: 1; /*!< [23..23] TIMER32_0 Clock Required (TIMER32_0_CL…
572 …__IO uint32_t TIMER32_1_CLK_REQ: 1; /*!< [24..24] TIMER32_1 Clock Required (TIMER32_1_CL…
573 …__IO uint32_t LED3_CLK_REQ: 1; /*!< [25..25] LED3 Clock Required (LED3_CLK_REQ) …
574 …__IO uint32_t PKE_CLK_REQ: 1; /*!< [26..26] PKE Clock Required …
575 …__IO uint32_t RNG_CLK_REQ: 1; /*!< [27..27] RNG Clock Required …
576 …__IO uint32_t AES_HASH_CLK_REQ: 1; /*!< [28..28] AES_HASH Clock Required …
577 …__IO uint32_t HTIMER_1_CLK_REQ: 1; /*!< [29..29] HTIMER 1 Clock Required (HTIMER_1_CLK_…
578 …__IO uint32_t CCTIMER_CLK_REQ: 1; /*!< [30..30] Capture Compare Timer Clock Required (…
580 …__IO uint32_t PWM9_CLK_REQ: 1; /*!< [31..31] PWM9 Clock Required (PWM9_CLK_REQ) …
585 …__IO uint32_t CLK_REQ_4; /*!< (@ 0x40080160) Clock Required 4 Register …
588 …__IO uint32_t PWM10_CLK_REQ: 1; /*!< [0..0] PWM10 Clock Required (PWM10_CLK_REQ) …
589 …__IO uint32_t PWM11_CLK_REQ: 1; /*!< [1..1] PWM11 Clock Required (PWM11_CLK_REQ) …
590 …__IO uint32_t CNT_TMER0_CLK_REQ: 1; /*!< [2..2] CNT_TMER0 Clock Required (CNT_TMER0_CLK_…
591 …__IO uint32_t CNT_TMER1_CLK_REQ: 1; /*!< [3..3] CNT_TMER1 Clock Required (CNT_TMER1_CLK_…
592 …__IO uint32_t CNT_TMER2_CLK_REQ: 1; /*!< [4..4] CNT_TMER2 Clock Required (CNT_TMER2_CLK_…
593 …__IO uint32_t CNT_TMER3_CLK_REQ: 1; /*!< [5..5] CNT_TMER3 Clock Required (CNT_TMER3_CLK_…
594 …__IO uint32_t RTOS_CLK_REQ: 1; /*!< [6..6] RTOS Clock Required (RTOS_CLK_REQ) …
595 …__IO uint32_t RPMPWM1_CLK_REQ: 1; /*!< [7..7] RPM-PWM1 Clock Required (RPMPWM1_CLK_REQ…
596 …__IO uint32_t QSPI_CLK_REQ: 1; /*!< [8..8] Quad SPI Clock Required …
597 …__IO uint32_t BCM1_CLK_REQ: 1; /*!< [9..9] BCM 1 Clock Required (BCM1_CLK_REQ) …
598 …__IO uint32_t RC_ID0_CLK_REQ: 1; /*!< [10..10] RC_ID0 Clock Required (RC_ID0_CLK_REQ)…
599 …__IO uint32_t RC_ID1_CLK_REQ: 1; /*!< [11..11] RC_ID1 Clock Required (RC_ID1_CLK_REQ)…
600 …__IO uint32_t RC_ID2_CLK_REQ: 1; /*!< [12..12] RC_ID2 Clock Required (RC_ID2_CLK_REQ)…
606 …__IO uint32_t RST_EN_0; /*!< (@ 0x40080170) Reset Enable 0 Register …
609 …__IO uint32_t JTAG_STAP_RST_EN: 1; /*!< [0..0] JTAG STAP Reset Enable …
610 …__IO uint32_t EFUSE_RST_EN: 1; /*!< [1..1] eFuse Reset Enable …
615 …__IO uint32_t RST_EN_1; /*!< (@ 0x40080174) Reset Enable 1 Register …
618 …__IO uint32_t INT_RST_EN : 1; /*!< [0..0] Interrupt Reset Enable …
619 …__IO uint32_t PECI_RST_EN: 1; /*!< [1..1] PECI Reset Enable …
620 …__IO uint32_t TACH0_RST_EN: 1; /*!< [2..2] TACH0 Reset Enable (TACH0_RST_EN) …
622 …__IO uint32_t PWM0_RST_EN: 1; /*!< [4..4] PWM0 Reset Enable (PWM0_RST_EN) …
623 …__IO uint32_t PMC_RST_EN : 1; /*!< [5..5] PMC Reset Enable (PMC_RST_EN) …
624 …__IO uint32_t DMA_RST_EN : 1; /*!< [6..6] DMA Reset Enable (DMA_RST_EN) …
625 …__IO uint32_t TFDP_RST_EN: 1; /*!< [7..7] TFDP Reset Enable (TFDP_RST_EN) …
626 …__IO uint32_t PROCESSOR_RST_EN: 1; /*!< [8..8] PROCESSOR Reset Enable (PROCESSOR_RST_EN…
627 …__IO uint32_t WDT_RST_EN : 1; /*!< [9..9] WDT Reset Enable (WDT_RST_EN) …
628 …__IO uint32_t SMB0_RST_EN: 1; /*!< [10..10] SMB0 Reset Enable (SMB0_RST_EN) …
629 …__IO uint32_t TACH1_RST_EN: 1; /*!< [11..11] TACH1 Reset Enable (TACH1_RST_EN) …
630 …__IO uint32_t TACH2_RST_EN: 1; /*!< [12..12] TACH2 Reset Enable (TACH2_RST_EN) …
632 …__IO uint32_t PWM1_RST_EN: 1; /*!< [20..20] PWM1 Reset Enable (PWM1_RST_EN) …
633 …__IO uint32_t PWM2_RST_EN: 1; /*!< [21..21] PWM2 Reset Enable (PWM2_RST_EN) …
634 …__IO uint32_t PWM3_RST_EN: 1; /*!< [22..22] PWM3 Reset Enable (PWM3_RST_EN) …
635 …__IO uint32_t PWM4_RST_EN: 1; /*!< [23..23] PWM4 Reset Enable (PWM4_RST_EN) …
636 …__IO uint32_t PWM5_RST_EN: 1; /*!< [24..24] PWM3 Reset Enable (PWM5_RST_EN) …
637 …__IO uint32_t PWM6_RST_EN: 1; /*!< [25..25] PWM3 Reset Enable (PWM6_RST_EN) …
638 …__IO uint32_t PWM7_RST_EN: 1; /*!< [26..26] PWM3 Reset Enable (PWM7_RST_EN) …
639 …__IO uint32_t PWM8_RST_EN: 1; /*!< [27..27] PWM3 Reset Enable (PWM8_RST_EN) …
641 …__IO uint32_t EC_REG_BANK_RST_EN: 1; /*!< [29..29] EC_REG_BANK Reset Enable (EC_REG_BANK_…
642 …__IO uint32_t TIMER16_0_RST_EN: 1; /*!< [30..30] TIMER16_0 Reset Enable (TIMER16_0_RST_…
643 …__IO uint32_t TIMER16_1_RST_EN: 1; /*!< [31..31] TIMER16_1 Reset Enable (TIMER16_1_RST_…
648 …__IO uint32_t RST_EN_2; /*!< (@ 0x40080178) Reset Enable 2 Register …
651 …__IO uint32_t LPC_RST_EN : 1; /*!< [0..0] LPC Reset Enable (LPC_RST_EN) …
652 …__IO uint32_t UART_0_RST_EN: 1; /*!< [1..1] UART 0 Reset Enable …
653 …__IO uint32_t UART_1_RST_EN: 1; /*!< [2..2] UART 1 Reset Enable …
655 …__IO uint32_t GLBL_CFG_RST_EN: 1; /*!< [12..12] GLBL_CFG (GLBL_CFG_RST_EN) …
656 …__IO uint32_t ACPI_EC_0_RST_EN: 1; /*!< [13..13] ACPI EC 0 Reset Enable (ACPI_EC_0_RST_…
657 …__IO uint32_t ACPI_EC_1_RST_EN: 1; /*!< [14..14] ACPI EC 1 Reset Enable (ACPI_EC_1_RST_…
658 …__IO uint32_t ACPI_PM1_RST_EN: 1; /*!< [15..15] ACPI PM1 Reset Enable (ACPI_PM1_RST_EN…
659 …__IO uint32_t KBCEM_RST_EN: 1; /*!< [16..16] 8042EM Reset Enable (8042EM_RST_EN) …
660 …__IO uint32_t MBX_RST_EN : 1; /*!< [17..17] Mailbox Reset Enable (8042EM_RST_EN) …
661 …__IO uint32_t RTC_RST_EN : 1; /*!< [18..18] RTC Reset Enable (RTC_RST_EN) …
662 …__IO uint32_t ESPI_RST_EN: 1; /*!< [19..19] eSPI Reset Enable …
664 …__IO uint32_t ACPI_EC_2_RST_EN: 1; /*!< [21..21] ACPI EC 2 Reset Enable (ACPI_EC_2_RST_…
665 …__IO uint32_t ACPI_EC_3_RST_EN: 1; /*!< [22..22] ACPI EC 3 Reset Enable (ACPI_EC_3_RST_…
666 …__IO uint32_t ACPI_EC_4_RST_EN: 1; /*!< [23..23] ACPI EC 4 Reset Enable (ACPI_EC_4_RST_…
668 …__IO uint32_t PORT80_0_RST_EN: 1; /*!< [25..25] Port 80 0 Reset Enable …
669 …__IO uint32_t PORT80_1_RST_EN: 1; /*!< [26..26] Port 80 1 Reset Enable …
674 …__IO uint32_t RST_EN_3; /*!< (@ 0x4008017C) Reset Enable 3 Register …
678 …__IO uint32_t ADC_RST_EN : 1; /*!< [3..3] ADC Reset Enable (ADC_RST_EN) …
680 …__IO uint32_t PS2_0_RST_EN: 1; /*!< [5..5] PS2_0 Reset Enable (PS2_0_RST_EN) …
681 …__IO uint32_t PS2_1_RST_EN: 1; /*!< [6..6] PS2_1 Reset Enable (PS2_1_RST_EN) …
682 …__IO uint32_t PS2_2_RST_EN: 1; /*!< [7..7] PS2_2 Reset Enable (PS2_2_RST_EN) …
684 …__IO uint32_t GP_SPI0_RST_EN: 1; /*!< [9..9] GP SPI0 Reset Enable (GP_SPI0_RST_EN) …
685 …__IO uint32_t HTIMER_0_RST_EN: 1; /*!< [10..10] HTIMER 0 Reset Enable (HTIMER_0_RST_EN…
686 …__IO uint32_t KEYSCAN_RST_EN: 1; /*!< [11..11] KEYSCAN Reset Enable (KEYSCAN_RST_EN) …
687 …__IO uint32_t RPMPWM0_RST_EN: 1; /*!< [12..12] RPM-PWM 0 Reset Enable (RPMPWM0_RST_EN…
688 …__IO uint32_t SMB1_RST_EN: 1; /*!< [13..13] SMB1 Reset Enable (SMB1_RST_EN) …
689 …__IO uint32_t SMB2_RST_EN: 1; /*!< [14..14] SMB2 Reset Enable (SMB2_RST_EN) …
690 …__IO uint32_t SMB3_RST_EN: 1; /*!< [15..15] SMB3 Reset Enable (SMB3_RST_EN) …
691 …__IO uint32_t LED0_RST_EN: 1; /*!< [16..16] LED0 Reset Enable (LED0_RST_EN) …
692 …__IO uint32_t LED1_RST_EN: 1; /*!< [17..17] LED1 Reset Enable (LED1_RST_EN) …
693 …__IO uint32_t LED2_RST_EN: 1; /*!< [18..18] LED2 Reset Enable (LED2_RST_EN) …
694 …__IO uint32_t BCM0_RST_EN: 1; /*!< [19..19] BCM 0 Reset Enable (BCM0_RST_EN) …
695 …__IO uint32_t GP_SPI1_RST_EN: 1; /*!< [20..20] GP SPI1 Reset Enable (GP_SPI1_RST_EN) …
696 …__IO uint32_t TIMER16_2_RST_EN: 1; /*!< [21..21] TIMER16_2_Reset Enable (TIMER16_2_RST_…
697 …__IO uint32_t TIMER16_3_RST_EN: 1; /*!< [22..22] TIMER16_3 Reset Enable (TIMER16_3_RST_…
698 …__IO uint32_t TIMER32_0_RST_EN: 1; /*!< [23..23] TIMER32_0 Reset Enable (TIMER32_0_RST_…
699 …__IO uint32_t TIMER32_1_RST_EN: 1; /*!< [24..24] TIMER32_1 Reset Enable (TIMER32_1_RST_…
700 …__IO uint32_t LED3_RST_EN: 1; /*!< [25..25] LED3 Reset Enable (LED3_RST_EN) …
701 …__IO uint32_t PKE_RST_EN : 1; /*!< [26..26] PKE Reset Enable …
702 …__IO uint32_t RNG_RST_EN : 1; /*!< [27..27] RNG Reset Enable …
703 …__IO uint32_t AES_HASH_RST_EN: 1; /*!< [28..28] AES_HASH Reset Enable …
704 …__IO uint32_t HTIMER_1_RST_EN: 1; /*!< [29..29] HTIMER 1 Reset Enable (HTIMER_1_RST_EN…
705 …__IO uint32_t CCTIMER_RST_EN: 1; /*!< [30..30] Capture Compare Timer Reset Enable (CC…
707 …__IO uint32_t PWM9_RST_EN: 1; /*!< [31..31] PWM9 Reset Enable (PWM9_RST_EN) …
712 …__IO uint32_t RST_EN_4; /*!< (@ 0x40080180) Reset Enable 4 Register …
715 …__IO uint32_t PWM10_RST_EN: 1; /*!< [0..0] PWM10 Reset Enable (PWM10_RST_EN) …
716 …__IO uint32_t PWM11_RST_EN: 1; /*!< [1..1] PWM11 Reset Enable (PWM11_RST_EN) …
717 …__IO uint32_t CNT_TMER0_RST_EN: 1; /*!< [2..2] CNT_TMER0 Reset Enable (CNT_TMER0_RST_EN…
718 …__IO uint32_t CNT_TMER1_RST_EN: 1; /*!< [3..3] CNT_TMER1 Reset Enable (CNT_TMER1_RST_EN…
719 …__IO uint32_t CNT_TMER2_RST_EN: 1; /*!< [4..4] CNT_TMER2 Reset Enable (CNT_TMER2_RST_EN…
720 …__IO uint32_t CNT_TMER3_RST_EN: 1; /*!< [5..5] CNT_TMER3 Reset Enable (CNT_TMER3_RST_EN…
721 …__IO uint32_t RTOS_RST_EN: 1; /*!< [6..6] RTOS Reset Enable (RTOS_RST_EN) …
722 …__IO uint32_t RPMPWM1_RST_EN: 1; /*!< [7..7] RPM-PWM1 Reset Enable (RPMPWM1_RST_EN) …
723 …__IO uint32_t QSPI_RST_EN: 1; /*!< [8..8] Quad SPI Reset Enable …
724 …__IO uint32_t BCM1_RST_EN: 1; /*!< [9..9] BCM 1 Reset Enable (BCM1_RST_EN) …
725 …__IO uint32_t RC_ID0_RST_EN: 1; /*!< [10..10] RC_ID0 Reset Enable (RC_ID0_RST_EN) …
726 …__IO uint32_t RC_ID1_RST_EN: 1; /*!< [11..11] RC_ID1 Reset Enable (RC_ID1_RST_EN) …
727 …__IO uint32_t RC_ID2_RST_EN: 1; /*!< [12..12] RC_ID2 Reset Enable (RC_ID2_RST_EN) …
745 …__IO uint8_t DMA_MAIN_CONTROL; /*!< (@ 0x40002400) Soft reset the entire module. …
749 __IO uint8_t ACTIVATE : 1; /*!< [0..0] Enable the blocks operation. (R/WS)
775 …__IO uint8_t DMA_CHANNEL_ACTIVATE; /*!< (@ 0x40002440) Enable this channel for operat…
780 …__IO uint8_t CHANNEL_ACTIVATE: 1; /*!< [0..0] Enable this channel for operation. The D…
788 …__IO uint32_t MEMORY_START_ADDRESS; /*!< (@ 0x40002444) This is the starting address…
790 …__IO uint32_t MEMORY_END_ADDRESS; /*!< (@ 0x40002448) This is the ending address f…
792 …__IO uint32_t DEVICE_ADDRESS; /*!< (@ 0x4000244C) This is the Master Device ad…
795 …__IO uint32_t CONTROL; /*!< (@ 0x40002450) DMA Channel N Control …
798 …__IO uint32_t RUN : 1; /*!< [0..0] This is a control field. Note: This bit …
803 __IO uint32_t REQUEST : 1; /*!< [1..1] This is a status field.
806 …__IO uint32_t DONE : 1; /*!< [2..2] This is a status signal. It is only vali…
812 …__IO uint32_t STATUS : 2; /*!< [3..4] This is a status signal. The status deco…
821 __IO uint32_t BUSY : 1; /*!< [5..5] This is a status signal.
825 …__IO uint32_t TX_DIRECTION: 1; /*!< [8..8] This determines the direction of the DMA…
830 …__IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< [9..15] This is the device that is connected …
838 …__IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< [16..16] This will enable an auto-increment to …
843 …__IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< [17..17] This will enable an auto-increment to …
848 …__IO uint32_t LOCK : 1; /*!< [18..18] This is used to lock the arbitration o…
853 …__IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< [19..19] This will Disable the Hardware Flow Co…
858 …__IO uint32_t TRANSFER_SIZE: 3; /*!< [20..22] This is the transfer size in Bytes of …
863 …__IO uint32_t TRANSFER_GO: 1; /*!< [24..24] This is used for the Firmware Flow Con…
865 …__IO uint32_t TRANSFER_ABORT: 1; /*!< [25..25] This is used to abort the current tran…
872 …__IO uint8_t INT_STATUS; /*!< (@ 0x40002454) DMA Channel N Interrupt Status…
875 …__IO uint8_t BUS_ERROR : 1; /*!< [0..0] This is an interrupt source register. Th…
878 …__IO uint8_t FLOW_CONTROL: 1; /*!< [1..1] This is an interrupt source register. Th…
885 …__IO uint8_t DONE : 1; /*!< [2..2] This is an interrupt source register. Th…
899 …__IO uint8_t INT_EN; /*!< (@ 0x40002458) DMA CHANNEL N INTERRUPT ENABLE…
902 …__IO uint8_t STATUS_ENABLE_BUS_ERROR: 1; /*!< [0..0] This is an interrupt enable for DMA Chan…
906 …__IO uint8_t STATUS_ENABLE_FLOW_CONTROL: 1;/*!< [1..1] This is an interrupt enable for DMA Chan…
910 …__IO uint8_t STATUS_ENABLE_DONE: 1; /*!< [2..2] This is an interrupt enable for DMA Chan…
919 …__IO uint32_t CRC_ENABLE; /*!< (@ 0x40002460) DMA CHANNEL N CRC ENABLE …
922 …__IO uint32_t CRC_MODE_ENABLE: 1; /*!< [0..0] 1=Enable the calculation of CRC-32 for D…
924 …__IO uint32_t CRC_POST_TRANSFER_ENABLE: 1; /*!< [1..1] The bit enables the transfer of the calc…
938 …__IO uint32_t CRC_DATA; /*!< (@ 0x40002464) DMA CHANNEL N CRC DATA …
941 …__IO uint32_t CRC : 32; /*!< [0..31] Writes to this register initialize the …
954 …__IO uint32_t CRC_POST_STATUS; /*!< (@ 0x40002468) DMA CHANNEL N CRC POST STATUS …
991 …__IO uint8_t DMA_CHANNEL_ACTIVATE; /*!< (@ 0x40002480) Enable this channel for operat…
996 …__IO uint8_t CHANNEL_ACTIVATE: 1; /*!< [0..0] Enable this channel for operation. The D…
1004 …__IO uint32_t MEMORY_START_ADDRESS; /*!< (@ 0x40002484) This is the starting address…
1006 …__IO uint32_t MEMORY_END_ADDRESS; /*!< (@ 0x40002488) This is the ending address f…
1008 …__IO uint32_t DEVICE_ADDRESS; /*!< (@ 0x4000248C) This is the Master Device ad…
1011 …__IO uint32_t CONTROL; /*!< (@ 0x40002490) DMA Channel N Control …
1014 …__IO uint32_t RUN : 1; /*!< [0..0] This is a control field. Note: This bit …
1019 __IO uint32_t REQUEST : 1; /*!< [1..1] This is a status field.
1022 …__IO uint32_t DONE : 1; /*!< [2..2] This is a status signal. It is only vali…
1028 …__IO uint32_t STATUS : 2; /*!< [3..4] This is a status signal. The status deco…
1037 __IO uint32_t BUSY : 1; /*!< [5..5] This is a status signal.
1041 …__IO uint32_t TX_DIRECTION: 1; /*!< [8..8] This determines the direction of the DMA…
1046 …__IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< [9..15] This is the device that is connected …
1054 …__IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< [16..16] This will enable an auto-increment to …
1059 …__IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< [17..17] This will enable an auto-increment to …
1064 …__IO uint32_t LOCK : 1; /*!< [18..18] This is used to lock the arbitration o…
1069 …__IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< [19..19] This will Disable the Hardware Flow Co…
1074 …__IO uint32_t TRANSFER_SIZE: 3; /*!< [20..22] This is the transfer size in Bytes of …
1079 …__IO uint32_t TRANSFER_GO: 1; /*!< [24..24] This is used for the Firmware Flow Con…
1081 …__IO uint32_t TRANSFER_ABORT: 1; /*!< [25..25] This is used to abort the current tran…
1088 …__IO uint8_t INT_STATUS; /*!< (@ 0x40002494) DMA Channel N Interrupt Status…
1091 …__IO uint8_t BUS_ERROR : 1; /*!< [0..0] This is an interrupt source register. Th…
1094 …__IO uint8_t FLOW_CONTROL: 1; /*!< [1..1] This is an interrupt source register. Th…
1101 …__IO uint8_t DONE : 1; /*!< [2..2] This is an interrupt source register. Th…
1115 …__IO uint8_t INT_EN; /*!< (@ 0x40002498) DMA CHANNEL N INTERRUPT ENABLE…
1118 …__IO uint8_t STATUS_ENABLE_BUS_ERROR: 1; /*!< [0..0] This is an interrupt enable for DMA Chan…
1122 …__IO uint8_t STATUS_ENABLE_FLOW_CONTROL: 1;/*!< [1..1] This is an interrupt enable for DMA Chan…
1126 …__IO uint8_t STATUS_ENABLE_DONE: 1; /*!< [2..2] This is an interrupt enable for DMA Chan…
1135 …__IO uint32_t FILL_ENABLE; /*!< (@ 0x400024A0) DMA CHANNEL N FILL ENABLE …
1138 …__IO uint32_t FILL_MODE_ENABLE: 1; /*!< [0..0] 1=Enable the calculation of CRC-32 for D…
1144 …__IO uint32_t FILL_DATA; /*!< (@ 0x400024A4) DMA CHANNEL N FILL DATA …
1147 …__IO uint32_t FILL_DATA : 32; /*!< [0..31] This is the data pattern used to fill m…
1152 …__IO uint32_t FILL_STATUS; /*!< (@ 0x400024A8) DMA CHANNEL N FILL STATUS …
1181 …__IO uint8_t DMA_CHANNEL_ACTIVATE; /*!< (@ 0x400024C0) Enable this channel for operat…
1186 …__IO uint8_t CHANNEL_ACTIVATE: 1; /*!< [0..0] Enable this channel for operation. The D…
1194 …__IO uint32_t MEMORY_START_ADDRESS; /*!< (@ 0x400024C4) This is the starting address…
1196 …__IO uint32_t MEMORY_END_ADDRESS; /*!< (@ 0x400024C8) This is the ending address f…
1198 …__IO uint32_t DEVICE_ADDRESS; /*!< (@ 0x400024CC) This is the Master Device ad…
1201 …__IO uint32_t CONTROL; /*!< (@ 0x400024D0) DMA Channel N Control …
1204 …__IO uint32_t RUN : 1; /*!< [0..0] This is a control field. Note: This bit …
1209 __IO uint32_t REQUEST : 1; /*!< [1..1] This is a status field.
1212 …__IO uint32_t DONE : 1; /*!< [2..2] This is a status signal. It is only vali…
1218 …__IO uint32_t STATUS : 2; /*!< [3..4] This is a status signal. The status deco…
1227 __IO uint32_t BUSY : 1; /*!< [5..5] This is a status signal.
1231 …__IO uint32_t TX_DIRECTION: 1; /*!< [8..8] This determines the direction of the DMA…
1236 …__IO uint32_t HARDWARE_FLOW_CONTROL_DEVICE: 7;/*!< [9..15] This is the device that is connected …
1244 …__IO uint32_t INCREMENT_MEM_ADDR: 1; /*!< [16..16] This will enable an auto-increment to …
1249 …__IO uint32_t INCREMENT_DEVICE_ADDR: 1; /*!< [17..17] This will enable an auto-increment to …
1254 …__IO uint32_t LOCK : 1; /*!< [18..18] This is used to lock the arbitration o…
1259 …__IO uint32_t DISABLE_HW_FLOW_CONTROL: 1; /*!< [19..19] This will Disable the Hardware Flow Co…
1264 …__IO uint32_t TRANSFER_SIZE: 3; /*!< [20..22] This is the transfer size in Bytes of …
1269 …__IO uint32_t TRANSFER_GO: 1; /*!< [24..24] This is used for the Firmware Flow Con…
1271 …__IO uint32_t TRANSFER_ABORT: 1; /*!< [25..25] This is used to abort the current tran…
1278 …__IO uint8_t INT_STATUS; /*!< (@ 0x400024D4) DMA Channel N Interrupt Status…
1281 …__IO uint8_t BUS_ERROR : 1; /*!< [0..0] This is an interrupt source register. Th…
1284 …__IO uint8_t FLOW_CONTROL: 1; /*!< [1..1] This is an interrupt source register. Th…
1291 …__IO uint8_t DONE : 1; /*!< [2..2] This is an interrupt source register. Th…
1305 …__IO uint8_t INT_EN; /*!< (@ 0x400024D8) DMA CHANNEL N INTERRUPT ENABLE…
1308 …__IO uint8_t STATUS_ENABLE_BUS_ERROR: 1; /*!< [0..0] This is an interrupt enable for DMA Chan…
1312 …__IO uint8_t STATUS_ENABLE_FLOW_CONTROL: 1;/*!< [1..1] This is an interrupt enable for DMA Chan…
1316 …__IO uint8_t STATUS_ENABLE_DONE: 1; /*!< [2..2] This is an interrupt enable for DMA Chan…
1339 …__IO uint32_t GIRQ08_SRC; /*!< (@ 0x4000E000) Status R/W1C …
1340 …__IO uint32_t GIRQ08_EN_SET; /*!< (@ 0x4000E004) Write to set source enables …
1342 …__IO uint32_t GIRQ08_EN_CLR; /*!< (@ 0x4000E00C) Write to clear source enable…
1344 …__IO uint32_t GIRQ09_SRC; /*!< (@ 0x4000E014) Status R/W1C …
1345 …__IO uint32_t GIRQ09_EN_SET; /*!< (@ 0x4000E018) Write to set source enables …
1347 …__IO uint32_t GIRQ09_EN_CLR; /*!< (@ 0x4000E020) Write to clear source enable…
1349 …__IO uint32_t GIRQ10_SRC; /*!< (@ 0x4000E028) Status R/W1C …
1350 …__IO uint32_t GIRQ10_EN_SET; /*!< (@ 0x4000E02C) Write to set source enables …
1352 …__IO uint32_t GIRQ10_EN_CLR; /*!< (@ 0x4000E034) Write to clear source enable…
1354 …__IO uint32_t GIRQ11_SRC; /*!< (@ 0x4000E03C) Status R/W1C …
1355 …__IO uint32_t GIRQ11_EN_SET; /*!< (@ 0x4000E040) Write to set source enables …
1357 …__IO uint32_t GIRQ11_EN_CLR; /*!< (@ 0x4000E048) Write to clear source enable…
1359 …__IO uint32_t GIRQ12_SRC; /*!< (@ 0x4000E050) Status R/W1C …
1360 …__IO uint32_t GIRQ12_EN_SET; /*!< (@ 0x4000E054) Write to set source enables …
1362 …__IO uint32_t GIRQ12_EN_CLR; /*!< (@ 0x4000E05C) Write to clear source enable…
1364 …__IO uint32_t GIRQ13_SRC; /*!< (@ 0x4000E064) Status R/W1C …
1365 …__IO uint32_t GIRQ13_EN_SET; /*!< (@ 0x4000E068) Write to set source enables …
1367 …__IO uint32_t GIRQ13_EN_CLR; /*!< (@ 0x4000E070) Write to clear source enable…
1369 …__IO uint32_t GIRQ14_SRC; /*!< (@ 0x4000E078) Status R/W1C …
1370 …__IO uint32_t GIRQ14_EN_SET; /*!< (@ 0x4000E07C) Write to set source enables …
1372 …__IO uint32_t GIRQ14_EN_CLR; /*!< (@ 0x4000E084) Write to clear source enable…
1374 …__IO uint32_t GIRQ15_SRC; /*!< (@ 0x4000E08C) Status R/W1C …
1375 …__IO uint32_t GIRQ15_EN_SET; /*!< (@ 0x4000E090) Write to set source enables …
1377 …__IO uint32_t GIRQ15_EN_CLR; /*!< (@ 0x4000E098) Write to clear source enable…
1379 …__IO uint32_t GIRQ16_SRC; /*!< (@ 0x4000E0A0) Status R/W1C …
1380 …__IO uint32_t GIRQ16_EN_SET; /*!< (@ 0x4000E0A4) Write to set source enables …
1382 …__IO uint32_t GIRQ16_EN_CLR; /*!< (@ 0x4000E0AC) Write to clear source enable…
1384 …__IO uint32_t GIRQ17_SRC; /*!< (@ 0x4000E0B4) Status R/W1C …
1385 …__IO uint32_t GIRQ17_EN_SET; /*!< (@ 0x4000E0B8) Write to set source enables …
1387 …__IO uint32_t GIRQ17_EN_CLR; /*!< (@ 0x4000E0C0) Write to clear source enable…
1389 …__IO uint32_t GIRQ18_SRC; /*!< (@ 0x4000E0C8) Status R/W1C …
1390 …__IO uint32_t GIRQ18_EN_SET; /*!< (@ 0x4000E0CC) Write to set source enables …
1392 …__IO uint32_t GIRQ18_EN_CLR; /*!< (@ 0x4000E0D4) Write to clear source enable…
1394 …__IO uint32_t GIRQ19_SRC; /*!< (@ 0x4000E0DC) Status R/W1C …
1395 …__IO uint32_t GIRQ19_EN_SET; /*!< (@ 0x4000E0E0) Write to set source enables …
1397 …__IO uint32_t GIRQ19_EN_CLR; /*!< (@ 0x4000E0E8) Write to clear source enable…
1399 …__IO uint32_t GIRQ20_SRC; /*!< (@ 0x4000E0F0) Status R/W1C …
1400 …__IO uint32_t GIRQ20_EN_SET; /*!< (@ 0x4000E0F4) Write to set source enables …
1402 …__IO uint32_t GIRQ20_EN_CLR; /*!< (@ 0x4000E0FC) Write to clear source enable…
1404 …__IO uint32_t GIRQ21_SRC; /*!< (@ 0x4000E104) Status R/W1C …
1405 …__IO uint32_t GIRQ21_EN_SET; /*!< (@ 0x4000E108) Write to set source enables …
1407 …__IO uint32_t GIRQ21_EN_CLR; /*!< (@ 0x4000E110) Write to clear source enable…
1409 …__IO uint32_t GIRQ22_SRC; /*!< (@ 0x4000E118) Status R/W1C …
1410 …__IO uint32_t GIRQ22_EN_SET; /*!< (@ 0x4000E11C) Write to set source enables …
1412 …__IO uint32_t GIRQ22_EN_CLR; /*!< (@ 0x4000E124) Write to clear source enable…
1414 …__IO uint32_t GIRQ23_SRC; /*!< (@ 0x4000E12C) Status R/W1C …
1415 …__IO uint32_t GIRQ23_EN_SET; /*!< (@ 0x4000E130) Write to set source enables …
1417 …__IO uint32_t GIRQ23_EN_CLR; /*!< (@ 0x4000E138) Write to clear source enable…
1419 …__IO uint32_t GIRQ24_SRC; /*!< (@ 0x4000E140) Status R/W1C …
1420 …__IO uint32_t GIRQ24_EN_SET; /*!< (@ 0x4000E144) Write to set source enables …
1422 …__IO uint32_t GIRQ24_EN_CLR; /*!< (@ 0x4000E14C) Write to clear source enable…
1424 …__IO uint32_t GIRQ25_SRC; /*!< (@ 0x4000E154) Status R/W1C …
1425 …__IO uint32_t GIRQ25_EN_SET; /*!< (@ 0x4000E158) Write to set source enables …
1427 …__IO uint32_t GIRQ25_EN_CLR; /*!< (@ 0x4000E160) Write to clear source enable…
1429 …__IO uint32_t GIRQ26_SRC; /*!< (@ 0x4000E168) Status R/W1C …
1430 …__IO uint32_t GIRQ26_EN_SET; /*!< (@ 0x4000E16C) Write to set source enables …
1432 …__IO uint32_t GIRQ26_EN_CLR; /*!< (@ 0x4000E174) Write to clear source enable…
1436 …__IO uint32_t BLOCK_ENABLE_SET; /*!< (@ 0x4000E200) Block Enable Set Register …
1439 …__IO uint32_t IRQ_VECTOR_ENABLE_SET: 31; /*!< [0..30] Each GIRQx bit can be individually enab…
1451 …__IO uint32_t BLOCK_ENABLE_CLEAR; /*!< (@ 0x4000E204) Block Enable Clear Register. …
1454 …__IO uint32_t IRQ_VECTOR_ENABLE_CLEAR: 31; /*!< [0..30] Each GIRQx bit can be individually disa…
1490 …__IO uint8_t INDEX; /*!< (@ 0x400F3000) The INDEX register, which is…
1493 …__IO uint8_t DATA_REG; /*!< (@ 0x400F3001) The DATA register, which is …
1509 …__IO uint32_t HOST_BUS_ERROR; /*!< (@ 0x400F3108) Host Bus Error Register …
1512 …__IO uint32_t LPC_ERR : 1; /*!< [0..0] A BAR conflict or an internal bus error …
1514 …__IO uint32_t EN_ERR : 1; /*!< [1..1] Internal bus errors will also cause LPC_…
1516 …__IO uint32_t BAR_ERR : 1; /*!< [2..2] a BAR conflict occurs on an LPC address.…
1517 …__IO uint32_t RUNTIME_ERR: 1; /*!< [3..3] EN_INTERNAL_ERR is 1 and an LPC I/O acce…
1520 …__IO uint32_t CONFIG_ERR : 1; /*!< [4..4] EN_INTERNAL_ERR is 1 and an LPC Configur…
1522 …__IO uint32_t DMA_ERR : 1; /*!< [5..5] EN_INTERNAL_ERR is 1 and an LPC DMA acce…
1532 …__IO uint32_t EC_SERIRQ; /*!< (@ 0x400F310C) If the LPC Logical Device is s…
1537 …__IO uint32_t EC_IRQ : 1; /*!< [0..0] This bit is used as the interrupt source…
1543 …__IO uint32_t CLK_CTRL; /*!< (@ 0x400F3110) Controls throughput of LPC tra…
1546 …__IO uint32_t CLOCK_CONTROL: 2; /*!< [0..1] This field controls when the host interf…
1558 …__IO uint32_t HANDSHAKE : 1; /*!< [2..2] This bit controls throughput of LPC tran…
1564 …__IO uint32_t BAR_INHIBIT; /*!< (@ 0x400F3120) When bit Di of BAR_Inhibit i…
1569 …__IO uint16_t BAR_INIT; /*!< (@ 0x400F3130) This field is loaded into th…
1574 …__IO uint32_t SRAM_EC_BAR_0; /*!< (@ 0x400F3140) SRAM EC BAR 0 …
1577 …__IO uint32_t SIZE : 4; /*!< [0..3] The number of address bits to pass uncha…
1586 …__IO uint32_t INHIBIT : 1; /*!< [7..7] Host access to the memory block is inhib…
1589 …__IO uint32_t AHB_BASE : 24; /*!< [8..31] These 24 bits define the base of a regi…
1601 …__IO uint32_t SRAM_EC_BAR_1; /*!< (@ 0x400F3144) SRAM EC BAR 1 …
1604 …__IO uint32_t SIZE : 4; /*!< [0..3] The number of address bits to pass uncha…
1613 …__IO uint32_t INHIBIT : 1; /*!< [7..7] Host access to the memory block is inhib…
1616 …__IO uint32_t AHB_BASE : 24; /*!< [8..31] These 24 bits define the base of a regi…
1629 …__IO uint8_t ACTIVATE; /*!< (@ 0x400F3330) The LPC Logical Device is powe…
1633 …__IO uint8_t ACTIVATE : 1; /*!< [0..0] When this bit is 0, the logical device i…
1646 …__IO uint8_t SIRQ[16]; /*!< (@ 0x400F3340) The LPC Controller implements …
1651 …__IO uint8_t FRAME : 6; /*!< [0..5] These six bits select the Logical Device…
1656 …__IO uint8_t DEVICE : 1; /*!< [6..6] This field should always be set to 0 in …
1658 …__IO uint8_t SELECT : 1; /*!< [7..7] If this bit is 0, the first interrupt si…
1670 …__IO uint32_t LPC_BAR; /*!< (@ 0x400F3360) LPC Interface BAR Register …
1673 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1678 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1685 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1687 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1693 …__IO uint32_t MBX_BAR; /*!< (@ 0x400F3364) Mailbox Registers Interface BA…
1696 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1701 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1708 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1710 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1716 …__IO uint32_t KBC_BAR; /*!< (@ 0x400F3368) Keyboard Controller (8042) BAR…
1719 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1724 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1731 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1733 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1739 …__IO uint32_t EC0_BAR; /*!< (@ 0x400F336C) ACPI EC Interface 0 BAR …
1742 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1747 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1754 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1756 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1762 …__IO uint32_t EC1_BAR; /*!< (@ 0x400F3370) ACPI EC Interface 1 BAR …
1765 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1770 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1777 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1779 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1785 …__IO uint32_t EC2_BAR; /*!< (@ 0x400F3374) ACPI EC Interface 2 BAR …
1788 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1793 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1800 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1802 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1808 …__IO uint32_t EC3_BAR; /*!< (@ 0x400F3378) ACPI EC Interface 3 BAR …
1811 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1816 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1823 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1825 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1831 …__IO uint32_t EC4_BAR; /*!< (@ 0x400F337C) ACPI EC Interface 4 BAR …
1834 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1839 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1846 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1848 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1854 …__IO uint32_t PM1_BAR; /*!< (@ 0x400F3380) ACPI PM1 Interface BAR …
1857 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1862 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1869 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1871 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1877 …__IO uint32_t LFK_BAR; /*!< (@ 0x400F3384) Legacy (Fast Keyboard) Interfa…
1880 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1885 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1892 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1894 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1900 …__IO uint32_t UART0_BAR; /*!< (@ 0x400F3388) UART 0 BAR Register …
1903 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1908 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1915 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1917 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1923 …__IO uint32_t UART1_BAR; /*!< (@ 0x400F338C) UART 1 BAR Register …
1926 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1931 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1938 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1940 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1946 …__IO uint32_t EMI0_BAR; /*!< (@ 0x400F3390) EM Interface 0 BAR …
1949 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1954 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1961 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1963 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1969 …__IO uint32_t EMI1_BAR; /*!< (@ 0x400F3394) EM Interface 1 BAR …
1972 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
1977 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
1984 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
1986 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
1992 …__IO uint32_t EMI2_BAR; /*!< (@ 0x400F3398) EM Interface 2 BAR …
1995 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
2000 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2007 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2009 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
2015 …__IO uint32_t PORT80_0_BAR; /*!< (@ 0x400F339C) BIOS Debug (Port 80) 0 BAR …
2018 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
2023 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2030 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2032 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
2038 …__IO uint32_t PORT80_1_BAR; /*!< (@ 0x400F33A0) BIOS Debug (Port 80) 1 BAR …
2041 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
2046 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2053 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2055 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
2061 …__IO uint32_t RTC_BAR; /*!< (@ 0x400F33A4) RTC Registers Interface BAR …
2064 …__IO uint32_t MASK : 8; /*!< [0..7] These 8 bits are used to mask off addres…
2069 …__IO uint32_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2076 …__IO uint32_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2078 …__IO uint32_t LPC_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match LPC I/…
2085 …__IO uint32_t SRAM_0_BAR_LPC_CONFIG_DW0; /*!< (@ 0x400F33B0) SRAM 0 BAR, LPC Configuration …
2090 …__IO uint32_t VALID : 1; /*!< [7..7] If this bit is 1, the SRAM Memory BAR is…
2097 …__IO uint32_t SRAM_0_BAR_LPC_CONFIG_DW1; /*!< (@ 0x400F33B4) SRAM 0 BAR, LPC Configuration …
2101 …__IO uint32_t LPC_HOST_ADDRESS: 32; /*!< [0..31] These 32 bits are used to match LPC Mem…
2107 …__IO uint32_t SRAM_1_BAR_LPC_CONFIG_DW0; /*!< (@ 0x400F33B8) SRAM 1 BAR, LPC Configuration …
2112 …__IO uint32_t VALID : 1; /*!< [7..7] If this bit is 1, the SRAM Memory BAR is…
2119 …__IO uint32_t SRAM_1_BAR_LPC_CONFIG_DW1; /*!< (@ 0x400F33BC) SRAM 1 BAR, LPC Configuration …
2124 …__IO uint32_t VALID : 1; /*!< [7..7] If this bit is 1, the SRAM Memory BAR is…
2131 …__IO uint16_t MBX_MEM_BAR_W0; /*!< (@ 0x400F33C0) Mailbox Registers I/F Memory B…
2134 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2138 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2144 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2150 …__IO uint16_t MBX_MEM_BAR_W1; /*!< (@ 0x400F33C2) Mailbox Registers I/F Memory B…
2153 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2159 …__IO uint16_t MBX_MEM_BAR_W2; /*!< (@ 0x400F33C4) Mailbox Registers I/F Memory B…
2162 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2168 …__IO uint16_t EC0_MEM_BAR_W0; /*!< (@ 0x400F33C6) ACPI EC Interface 0 Memory BAR…
2171 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2175 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2181 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2187 …__IO uint16_t EC0_MEM_BAR_W1; /*!< (@ 0x400F33C8) ACPI EC Interface 0 Memory BAR…
2190 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2196 …__IO uint16_t EC0_MEM_BAR_W2; /*!< (@ 0x400F33CA) ACPI EC Interface 0 Memory BAR…
2199 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2205 …__IO uint16_t EC1_MEM_BAR_W0; /*!< (@ 0x400F33CC) ACPI EC Interface 1 Memory BAR…
2208 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2212 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2218 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2224 …__IO uint16_t EC1_MEM_BAR_W1; /*!< (@ 0x400F33CE) ACPI EC Interface 1 Memory BAR…
2227 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2233 …__IO uint16_t EC1_MEM_BAR_W2; /*!< (@ 0x400F33D0) ACPI EC Interface 1 Memory BAR…
2236 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2242 …__IO uint16_t EC2_MEM_BAR_W0; /*!< (@ 0x400F33D2) ACPI EC Interface 2 Memory BAR…
2245 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2249 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2255 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2261 …__IO uint16_t EC2_MEM_BAR_W1; /*!< (@ 0x400F33D4) ACPI EC Interface 2 Memory BAR…
2264 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2270 …__IO uint16_t EC2_MEM_BAR_W2; /*!< (@ 0x400F33D6) ACPI EC Interface 2 Memory BAR…
2273 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2279 …__IO uint16_t EC3_MEM_BAR_W0; /*!< (@ 0x400F33D8) ACPI EC Interface 3 Memory BAR…
2282 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2286 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2292 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2298 …__IO uint16_t EC3_MEM_BAR_W1; /*!< (@ 0x400F33DA) ACPI EC Interface 3 Memory BAR…
2301 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2307 …__IO uint16_t EC3_MEM_BAR_W2; /*!< (@ 0x400F33DC) ACPI EC Interface 3 Memory BAR…
2310 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2316 …__IO uint16_t EC4_MEM_BAR_W0; /*!< (@ 0x400F33DE) ACPI EC Interface 4 Memory BAR…
2319 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2323 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2329 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2335 …__IO uint16_t EC4_MEM_BAR_W1; /*!< (@ 0x400F33E0) ACPI EC Interface 4 Memory BAR…
2338 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2344 …__IO uint16_t EC4_MEM_BAR_W2; /*!< (@ 0x400F33E2) ACPI EC Interface 4 Memory BAR…
2347 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2353 …__IO uint16_t EMI0_MEM_BAR_W0; /*!< (@ 0x400F33E4) EM Interface 0 Memory BAR (WOR…
2356 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2360 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2366 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2372 …__IO uint16_t EMI0_MEM_BAR_W1; /*!< (@ 0x400F33E6) EM Interface 0 Memory BAR (WOR…
2375 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2381 …__IO uint16_t EMI0_MEM_BAR_W2; /*!< (@ 0x400F33E8) EM Interface 0 Memory BAR (WOR…
2384 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2390 …__IO uint16_t EMI1_MEM_BAR_W0; /*!< (@ 0x400F33EA) EM Interface 1 Memory BAR (WOR…
2393 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2397 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2403 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2409 …__IO uint16_t EMI1_MEM_BAR_W1; /*!< (@ 0x400F33EC) EM Interface 1 Memory BAR (WOR…
2412 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2418 …__IO uint16_t EMI1_MEM_BAR_W2; /*!< (@ 0x400F33EE) EM Interface 1 Memory BAR (WOR…
2421 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2427 …__IO uint16_t EMI2_MEM_BAR_W0; /*!< (@ 0x400F33F0) EM Interface 2 Memory BAR (DWO…
2430 …__IO uint16_t MASK : 8; /*!< [0..7] These bits are used to mask off address …
2434 …__IO uint16_t FRAME : 6; /*!< [8..13] These 6 bits are used to specify a logi…
2440 …__IO uint16_t VALID : 1; /*!< [15..15] If this bit is 1, the BAR is valid and…
2446 …__IO uint16_t EMI2_MEM_BAR_W1; /*!< (@ 0x400F33F2) EM Interface 2 Memory BAR (WOR…
2449 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32 bit address t…
2455 …__IO uint16_t EMI2_MEM_BAR_W2; /*!< (@ 0x400F33F4) EM Interface 2 Memory BAR (WOR…
2458 …__IO uint16_t LPC_HOST_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32 bit address t…
2478 …__IO uint8_t INDEX; /*!< (@ 0x400F3400) The INDEX register, which is…
2481 …__IO uint8_t DATA_REG; /*!< (@ 0x400F3401) The DATA register, which is …
2543 …__IO uint32_t PC_STATUS; /*!< (@ 0x400F3514) Peripheral Channel Status Regi…
2546 …__IO uint32_t PC_VIRTUAL_READ: 1; /*!< [0..0] This bit is set whenever a eSPI read tra…
2550 …__IO uint32_t PC_VIRTUAL_WRITE: 1; /*!< [1..1] This bit is set whenever a eSPI write tr…
2562 …__IO uint32_t PC_BUS_ERROR: 1; /*!< [16..16] This bit is set to '1' whenever an eSP…
2566 …__IO uint32_t BAR_CONFLICT: 1; /*!< [17..17] This bit is set to '1' whenever a BAR …
2574 …__IO uint32_t PC_ENABLE_CHANGE: 1; /*!< [25..25] This bit is set to '1' whenever the fi…
2583 …__IO uint32_t PC_MASTERING_ENABLE_CHANGE: 1;/*!< [28..28] This bit is set to '1' whenever the fi…
2590 …__IO uint32_t PC_INT_ENABLE; /*!< (@ 0x400F3518) Peripheral Channel Interrupt E…
2594 …__IO uint32_t PC_VIRTUAL_READ_ENABLE: 1; /*!< [0..0] When this bit is '1' an interrupt is gen…
2599 …__IO uint32_t PC_VIRTUAL_WRITE_ENABLE: 1; /*!< [1..1] When this bit is '1' an interrupt is gen…
2605 …__IO uint32_t PC_BUS_ERROR_ENABLE: 1; /*!< [16..16] When this bit is '1' an interrupt is g…
2610 …__IO uint32_t BAR_CONFLICT_ENABLE: 1; /*!< [17..17] When this bit is '1' an interrupt is g…
2616 …__IO uint32_t PC_ENABLE_CHANGE_ENABLE: 1; /*!< [25..25] When this bit is '1' an interrupt is g…
2622 …__IO uint32_t PC_MASTERING_ENABLE_CHANGE_ENABLE: 1;/*!< [28..28] When this bit is '1' an interru…
2632 …__IO uint32_t BAR_INHIBIT_DW0; /*!< (@ 0x400F3520) BAR Inhibit Register (DWord 0)…
2635 …__IO uint32_t BAR_INHIBIT_LSDW: 32; /*!< [0..31] When bit Di of BAR_Inhibit is 1, the BA…
2645 …__IO uint32_t BAR_INHIBIT_DW1; /*!< (@ 0x400F3524) BAR Inhibit Register (DWord 1)…
2648 …__IO uint32_t BAR_INHIBIT_MSDW: 32; /*!< [0..31] When bit Di of BAR_Inhibit is 1, the BA…
2658 …__IO uint32_t ESPI_BAR_INIT; /*!< (@ 0x400F3528) eSPI BAR Init Register …
2661 …__IO uint32_t BAR_INIT : 16; /*!< [0..15] This field is loaded into the Base Addr…
2668 …__IO uint32_t EC_IRQ; /*!< (@ 0x400F352C) EC IRQ Register …
2671 …__IO uint32_t EC_IRQ : 1; /*!< [0..0] This bit can be used as a firmware-contr…
2681 …__IO uint32_t ESPI_IO_BASE_ADDRESS; /*!< (@ 0x400F3534) eSPI I/O Base Address Register…
2696 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2704 …__IO uint32_t ESPI_MEM_BASE_ADDRESS; /*!< (@ 0x400F3538) eSPI Memory Base Address Regis…
2719 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2727 …__IO uint32_t MBX_BASE_ADDRESS; /*!< (@ 0x400F353C) Mailbox BAR Register …
2742 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2750 …__IO uint32_t EM8042_BASE_ADDRESS; /*!< (@ 0x400F3540) 8042 Emulated Keyboard Control…
2766 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2774 …__IO uint32_t ACPI_EC_0_BASE_ADDRESS; /*!< (@ 0x400F3544) ACPI EC Channel 0 Register …
2789 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2797 …__IO uint32_t ACPI_EC_1_BASE_ADDRESS; /*!< (@ 0x400F3548) ACPI EC Channel 1 BAR Register…
2812 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2820 …__IO uint32_t ACPI_EC_2_BASE_ADDRESS; /*!< (@ 0x400F354C) I/O Base Address Register …
2835 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2843 …__IO uint32_t ACPI_EC_3_BASE_ADDRESS; /*!< (@ 0x400F3550) I/O Base Address Register …
2858 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2866 …__IO uint32_t ACPI_EC_4_BASE_ADDRESS; /*!< (@ 0x400F3554) I/O Base Address Register …
2881 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2889 …__IO uint32_t ACPI_PM1_BASE_ADDRESS; /*!< (@ 0x400F3558) I/O Base Address Register …
2904 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2912 …__IO uint32_t FAST_KDB_BASE_ADDRESS; /*!< (@ 0x400F355C) I/O Base Address Register …
2927 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2935 …__IO uint32_t UART_0_BASE_ADDRESS; /*!< (@ 0x400F3560) I/O Base Address Register …
2950 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2958 …__IO uint32_t UART_1_BASE_ADDRESS; /*!< (@ 0x400F3564) I/O Base Address Register …
2973 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
2981 …__IO uint32_t EMI_0_BASE_ADDRESS; /*!< (@ 0x400F3568) I/O Base Address Register …
2996 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
3004 …__IO uint32_t EMI_1_BASE_ADDRESS; /*!< (@ 0x400F356C) I/O Base Address Register …
3019 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
3027 …__IO uint32_t EMI_2_BASE_ADDRESS; /*!< (@ 0x400F3570) I/O Base Address Register …
3042 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
3050 …__IO uint32_t PORT80_0_BASE_ADDRESS; /*!< (@ 0x400F3574) I/O Base Address Register …
3065 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
3073 …__IO uint32_t PORT80_1_BASE_ADDRESS; /*!< (@ 0x400F3578) I/O Base Address Register …
3088 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
3096 …__IO uint32_t RTC_BASE_ADDRESS; /*!< (@ 0x400F357C) I/O Base Address Register …
3111 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
3120 …__IO uint32_t LTR_PERIPHERAL_STATUS; /*!< (@ 0x400F3620) LTR Peripheral Status Register…
3123 …__IO uint32_t TRANSMIT_DONE_STATUS: 1; /*!< [0..0] This bit is set to '1' whenever a Transm…
3127 …__IO uint32_t START_OVERRUN_STATUS: 1; /*!< [3..3] A Start was attempted while the TRANSMIT…
3130 …__IO uint32_t DISABLED_BY_HOST_STATUS: 1; /*!< [4..4] A '1' in this bit indicates that the las…
3149 …__IO uint32_t LTR_PERIPHERAL_ENABLE; /*!< (@ 0x400F3624) LTR Peripheral Enable Register…
3152 …__IO uint32_t TRANSMIT_DONE_INT_ENABLE: 1; /*!< [0..0] When this bit is '1' an interrupt is gen…
3161 …__IO uint32_t LTR_PERIPHERAL_CONTROL; /*!< (@ 0x400F3628) LTR Peripheral Control Registe…
3171 …__IO uint32_t OUTGOING_TAG: 4; /*!< [8..11] This 4-bit value will be inserted as th…
3179 …__IO uint32_t LTR_PERIPHERAL_MESSAGE; /*!< (@ 0x400F362C) LTR Peripheral Message Registe…
3182 …__IO uint32_t VALUE : 10; /*!< [0..9] This field declares a time, in units exp…
3186 …__IO uint32_t SCALE : 3; /*!< [10..12] This field declares the time unit expr…
3188 …__IO uint32_t RESERVED_TRANSMITTED_BITS: 2; /*!< [13..14] These bits are Read/Write, but are und…
3193 …__IO uint32_t REQUIRED_BIT: 1; /*!< [15..15] 1 = Maximum latency tolerated is defin…
3201 …__IO uint32_t OOB_RECEIVE_ADDRESS; /*!< (@ 0x400F3640) OOB Channel Receive Address Re…
3205 …__IO uint32_t RECEIVE_BUFFER_ADDRESS: 30; /*!< [2..31] This field must be initialized to conta…
3212 …__IO uint32_t OOB_TRANSMIT_ADDRESS; /*!< (@ 0x400F3648) OOB Channel Transmit Address R…
3216 …__IO uint32_t TRANSMIT_BUFFER_ADDRESS: 30; /*!< [2..31] Before starting an OOB Transmit, this f…
3225 …__IO uint32_t OOB_RECEIVE_LENGTH; /*!< (@ 0x400F3650) OOB Channel Receive Length Reg…
3234 …__IO uint32_t RECEIVE_BUFFER_LENGTH: 13; /*!< [16..28] Before setting the Receive Enable bit …
3249 …__IO uint32_t OOB_TRANSMIT_LENGTH; /*!< (@ 0x400F3654) OOB Channel Transmit Length Re…
3252 …__IO uint32_t TRANSMIT_MESSAGE_LENGTH: 13; /*!< [0..12] This 13-bit field declares how many byt…
3261 …__IO uint32_t OOB_RECEIVE_CONTROL; /*!< (@ 0x400F3658) OOB Channel Receive Control Re…
3283 …__IO uint32_t OOB_RECEIVE_INT_ENABLE; /*!< (@ 0x400F365C) OOB Channel Receive Interrupt …
3287 …__IO uint32_t RECEIVE_INTERRUPT_ENABLE: 1; /*!< [0..0] When this bit is '1' an interrupt is gen…
3295 …__IO uint32_t OOB_RECEIVE_STATUS; /*!< (@ 0x400F3660) OOB Channel Receive Status Reg…
3298 …__IO uint32_t RECEIVE_DONE_STATUS: 1; /*!< [0..0] This bit is set to '1' whenever the RECE…
3304 …__IO uint32_t INTERNAL_BUS_ERROR_STATUS: 1; /*!< [1..1] This bit is set to '1' whenever the chan…
3310 …__IO uint32_t OVERRUN_STATUS: 1; /*!< [2..2] This bit is set to '1' whenever an incom…
3332 …__IO uint32_t OOB_TRANSMIT_CONTROL; /*!< (@ 0x400F3664) OOB Channel Transmit Control R…
3343 …__IO uint32_t OUTGOING_TAG: 4; /*!< [8..11] This 4-bit value will be inserted as th…
3349 …__IO uint32_t OOB_TRANSMIT_INT_ENABLE; /*!< (@ 0x400F3668) OOB Channel Transmit Interrupt…
3353 …__IO uint32_t TRANSMIT_DONE_INTERRUPT_ENABLE: 1;/*!< [0..0] When this bit is '1' an interrupt is…
3357 …__IO uint32_t CHANNEL_ENABLE_CHANGE_INTERRUPT_ENABLE: 1;/*!< [1..1] When this bit is '1' an inte…
3365 …__IO uint32_t OOB_TRANSMIT_STATUS; /*!< (@ 0x400F366C) OOB Channel Transmit Status Re…
3368 …__IO uint32_t TRANSMIT_DONE_STATUS: 1; /*!< [0..0] This bit is set to '1' whenever a Transm…
3371 …__IO uint32_t CHANNEL_ENABLE_CHANGE_STATUS: 1;/*!< [1..1] This bit is set to '1' whenever the eS…
3375 …__IO uint32_t INTERNAL_BUS_ERROR_STATUS: 1; /*!< [2..2] This error flag indicates an internal bu…
3377 …__IO uint32_t START_OVERRUN_STATUS: 1; /*!< [3..3] This error flag indicates a Start was at…
3381 …__IO uint32_t BAD_REQUEST: 1; /*!< [5..5] This bit is intended for any situation w…
3405 …__IO uint32_t FLASH_CH_FLASH_ADDRESS; /*!< (@ 0x400F3680) Flash Access Channel Flash Add…
3408 …__IO uint32_t FLASH_ADDRESS: 32; /*!< [0..31] Before starting a Flash access, this fi…
3416 …__IO uint32_t FLASH_CH_BUFFER_ADDRESS; /*!< (@ 0x400F3688) Flash Access Channel Buffer Ad…
3420 …__IO uint32_t BUFFER_ADDRESS: 32; /*!< [0..31] Before starting a Flash access, this fi…
3428 …__IO uint32_t FLASH_CH_TRANSFER_LENGTH; /*!< (@ 0x400F3690) Flash Access Channel Transfer …
3432 …__IO uint32_t TRANSFER_LENGTH: 32; /*!< [0..31] Before starting a Flash access, this fi…
3442 …__IO uint32_t FLASH_CH_CONTROL; /*!< (@ 0x400F3694) Flash Access Channel Control R…
3445 …__IO uint32_t FLASH_START: 1; /*!< [0..0] A write of '1' to this bit starts the tr…
3451 …__IO uint32_t FUNCTION : 2; /*!< [2..3] This bit selects the requested Flash fun…
3456 …__IO uint32_t TAG : 4; /*!< [4..7] This field should always be written to z…
3476 …__IO uint32_t FLASH_CH_INT_ENABLE; /*!< (@ 0x400F3698) Flash Access Channel Interrupt…
3480 …__IO uint32_t DONE_INTERRUPT_ENABLE: 1; /*!< [0..0] When this bit is '1' an interrupt is gen…
3484 …__IO uint32_t FLASH_ENABLE_STATUS_CHANGE_INTERRUPT_ENABLE: 1;/*!< [1..1] When this bit is '1' an…
3544 …__IO uint32_t FLASH_CH_STATUS; /*!< (@ 0x400F36A0) Flash Access Channel Status Re…
3555 …__IO uint32_t CHANNEL_ENABLE_CHANGE_STATUS: 1;/*!< [1..1] 0=Flash Access Enable bit in eSPI Conf…
3562 …__IO uint32_t DONE : 1; /*!< [2..2] 1=Channel is done=Busy bit has been clea…
3566 …__IO uint32_t DISABLED_BY_MASTER: 1; /*!< [3..3] This bit is set to '1' if the Flash Chan…
3571 …__IO uint32_t INTERNAL_BUS_ERROR: 1; /*!< [4..4] This bit is set to '1' if the internal b…
3576 …__IO uint32_t ABORTED_BY_SLAVE: 1; /*!< [5..5] This bit is set to '1' if the Abort bit …
3582 …__IO uint32_t DATA_OVERRUN: 1; /*!< [6..6] This bit is set to '1' by a SUCCESSFUL C…
3590 …__IO uint32_t INCOMPLETE : 1; /*!< [7..7] This bit is set to '1' by a SUCCESSFUL C…
3598 …__IO uint32_t FAIL : 1; /*!< [8..8] This bit is set to '1' by an explicit UN…
3605 …__IO uint32_t START_OVERFLOW: 1; /*!< [9..9] This bit is set if a command (initiated …
3617 …__IO uint32_t BAD_REQUEST: 1; /*!< [11..11] This bit is set to '1' when a firmware…
3638 …__IO uint8_t ESPI_CAPABILITIES_ID; /*!< (@ 0x400F36E0) eSPI Capabilities ID Register …
3641 …__IO uint8_t ESPI_DEVICE_ID: 8; /*!< [0..7] The default value should not be changed.…
3646 …__IO uint8_t ESPI_GLOBAL_CAPABILITIES_0; /*!< (@ 0x400F36E1) eSPI Capabilities Global Capab…
3650 …__IO uint8_t PERIPHERAL_CHANNEL_SUPPORTED: 1;/*!< [0..0] 1=Peripheral Channel is supported by t…
3652 …__IO uint8_t VIRTUAL_WIRE_CHANNEL_SUPPORTED: 1;/*!< [1..1] 1=Virtual Wire Channel is supported …
3654 …__IO uint8_t OOB_MESSAGE_CHANNEL_SUPPORTED: 1;/*!< [2..2] 1=OOB Message Channel is supported by…
3656 …__IO uint8_t FLASH_ACCESS_CHANNEL_SUPPORTED: 1;/*!< [3..3] 1=Flash Access Channel is supported …
3662 …__IO uint8_t ESPI_GLOBAL_CAPABILITIES_1; /*!< (@ 0x400F36E2) eSPI Capabilities Global Capab…
3666 …__IO uint8_t MAXIMUM_FREQUENCY_SUPPORTED: 3;/*!< [0..2] This field identifies the maximum frequ…
3679 …__IO uint8_t IO_MODE_SUPPORTED: 2; /*!< [4..5] This field identifies the I/O modes supp…
3691 …__IO uint8_t ESPI_PC_CAPABILITIES; /*!< (@ 0x400F36E3) eSPI Peripheral Channel Capabi…
3695 …__IO uint8_t PC_MAXIMUM_PAYLOAD_SIZE_SUPPORTED: 3;/*!< [0..2] This field identifies the maximum…
3708 …__IO uint8_t ESPI_VWIRE_CAPABILITIES; /*!< (@ 0x400F36E4) eSPI Virtual Wire Channel Capa…
3712 …__IO uint8_t MAXIMUM_VIRTUAL_WIRE_COUNT_SUPPORTED: 6;/*!< [0..5] This field identifies the maxi…
3722 …__IO uint8_t ESPI_OOB_CAPABILITIES; /*!< (@ 0x400F36E5) eSPI OOB Channel Capabilities …
3725 …__IO uint8_t OOB_MAXIMUM_PAYLOAD_SIZE_SUPPORTED: 3;/*!< [0..2] This field identifies the maximu…
3738 …__IO uint8_t ESPI_FLASH_CAPABILITIES; /*!< (@ 0x400F36E6) eSPI Flash Channel Capabilitie…
3741 …__IO uint8_t FLASH_MAXIMUM_PAYLOAD_SIZE_SUPPORTED: 3;/*!< [0..2] This field identifies the maxi…
3751 …__IO uint8_t SHARING_MODE_SUPPORTED: 1; /*!< [4..4] This field identifies the flash sharing …
3761 …__IO uint8_t ESPI_PERIPHERAL_READY; /*!< (@ 0x400F36E7) eSPI Peripheral Channel Ready …
3764 …__IO uint8_t PERIPHERAL_CHANNEL_READY: 1; /*!< [0..0] Firmware sets this bit to '1' to inform …
3780 …__IO uint8_t ESPI_OOB_READY; /*!< (@ 0x400F36E8) eSPI OOB Channel Ready Registe…
3783 …__IO uint8_t OOB_CHANNEL_READY: 1; /*!< [0..0] Firmware sets this bit to '1' to inform …
3798 …__IO uint8_t ESPI_FLASH_READY; /*!< (@ 0x400F36E9) eSPI Flash Channel Ready Regis…
3801 …__IO uint8_t FLASH_CHANNEL_READY: 1; /*!< [0..0] Firmware sets this bit to '1' to inform …
3815 …__IO uint8_t ESPI_RESET_INT_STATUS; /*!< (@ 0x400F36EA) eSPI Reset Interrupt Status Re…
3818 …__IO uint8_t ESPI_RESET_INTERRUPT_STATUS: 1;/*!< [0..0] This bit is set to '1' whenever the ESP…
3832 …__IO uint8_t ESPI_RESET_INT_ENABLE; /*!< (@ 0x400F36EB) eSPI Reset Interrupt Enable Re…
3835 …__IO uint8_t ESPI_RESET_INTERRUPT_ENABLE: 1;/*!< [0..0] 1=The RESET_ESPI Interrupt will be asse…
3843 …__IO uint8_t PLTRST_SOURCE; /*!< (@ 0x400F36EC) PLTRST Source Register …
3846 …__IO uint8_t PLTRST_SRC : 1; /*!< [0..0] 1=The PLTRST reset signal is determined …
3854 …__IO uint8_t ESPI_VWIRE_READY; /*!< (@ 0x400F36ED) eSPI Virtual Wire Channel Read…
3857 …__IO uint8_t VWIRE_CHANNEL_READY: 1; /*!< [0..0] Firmware sets this bit to '1' to inform …
3873 …__IO uint8_t ESPI_ACTIVATE; /*!< (@ 0x400F3730) eSPI Activate Register …
3876 …__IO uint8_t ACTIVATE : 1; /*!< [0..0] 1=Activate. When this bit is '1', the eS…
3888 …__IO uint32_t ESPI_IO_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3734) eSPI I/O Base Address Configur…
3892 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3895 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3901 …__IO uint32_t ESPI_MEM_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3738) eSPI Memory Base Address Confi…
3905 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3908 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3914 …__IO uint32_t MBX_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F373C) Mailbox Base Address Configura…
3917 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3920 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3926 …__IO uint32_t EM8042_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3740) 8042 Emulated Keyboard Control…
3930 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3933 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3939 …__IO uint32_t ACPI_EC_0_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3744) ACPI EC 0 Base Address Configu…
3943 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3946 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3952 …__IO uint32_t ACPI_EC_1_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3748) ACPI EC 1 Base Address Configu…
3956 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3959 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3965 …__IO uint32_t ACPI_EC_2_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F374C) ACPI EC 2 Base Address Configu…
3969 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3972 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3978 …__IO uint32_t ACPI_EC_3_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3750) ACPI EC 3 Base Address Configu…
3982 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3985 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
3991 …__IO uint32_t ACPI_EC_4_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3754) ACPI EC 4 Base Address Configu…
3995 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
3998 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4004 …__IO uint32_t ACPI_PM1_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3758) ACPI PM1 Base Address Configur…
4008 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4011 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4017 …__IO uint32_t FAST_KBD_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F375C) I/O Base Address Configuration…
4020 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4023 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4029 …__IO uint32_t UART_0_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3760) UART 0 Base Address Configurat…
4032 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4035 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4041 …__IO uint32_t UART_1_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3764) UART 1 Base Address Configurat…
4044 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4047 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4053 …__IO uint32_t EMI_0_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3768) Embedded Memory Interface (EMI…
4057 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4060 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4066 …__IO uint32_t EMI_1_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F376C) Embedded Memory Interface (EMI…
4070 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4073 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4079 …__IO uint32_t EMI_2_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3770) Embedded Memory Interface (EMI…
4083 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4086 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4092 …__IO uint32_t PORT80_0_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3774) BIOS Debug Port (Port 80) 0 BA…
4096 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4099 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4105 …__IO uint32_t PORT80_1_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F3778) BIOS Debug Port (Port 80) 1 BA…
4109 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4112 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4118 …__IO uint32_t RTC_BAR_CONFIG_ADDRESS; /*!< (@ 0x400F377C) RTC BAR Config Register …
4121 …__IO uint32_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4124 …__IO uint32_t ESPI_HOST_ADDRESS: 16; /*!< [16..31] These 16 bits are used to match eSPI I…
4131 …__IO uint8_t MBX_HOST_SIRQ_IRQ__SELECT; /*!< (@ 0x400F37AC) Mailbox (MBX_Host_SIRQ Interru…
4135 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4144 …__IO uint8_t MBX_HOST_SMI_IRQ_SELECT; /*!< (@ 0x400F37AD) Mailbox (MBX_Host_SMI Interrup…
4148 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4157 …__IO uint8_t KIRQ_8042_IRQ_SELECT; /*!< (@ 0x400F37AE) 8042 (KIRQ Interrupt) Selectio…
4160 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4169 …__IO uint8_t MIRQ_8042_IRQ_SELECT; /*!< (@ 0x400F37AF) 8042 (MIRQ Interrupt) Selectio…
4172 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4181 …__IO uint8_t ACPI_EC_0_OBF_IRQ_SELECT; /*!< (@ 0x400F37B0) ACPI EC 0 (EC_OBF Interrupt) S…
4185 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4194 …__IO uint8_t ACPI_EC_1_OBF_IRQ_SELECT; /*!< (@ 0x400F37B1) ACPI EC 1 (EC_OBF Interrupt) S…
4198 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4207 …__IO uint8_t ACPI_EC_2_OBF_IRQ_SELECT; /*!< (@ 0x400F37B2) ACPI EC 2 (EC_OBF Interrupt) S…
4211 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4220 …__IO uint8_t ACPI_EC_3_OBF_IRQ_SELECT; /*!< (@ 0x400F37B3) ACPI EC 3 (EC_OBF Interrupt) S…
4224 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4233 …__IO uint8_t ACPI_EC_4_OBF_IRQ_SELECT; /*!< (@ 0x400F37B4) ACPI EC 4 (EC_OBF Interrupt) S…
4237 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4246 …__IO uint8_t UART_0_IRQ_SELECT; /*!< (@ 0x400F37B5) UART 0 (UART Interrupt) Select…
4249 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4258 …__IO uint8_t UART_1_IRQ_SELECT; /*!< (@ 0x400F37B6) UART 1 (UART Interrupt) Select…
4261 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4270 …__IO uint8_t EMI_0_HOST_IRQ_SELECT; /*!< (@ 0x400F37B7) EMI 0 (Host Event Interrupt) S…
4274 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4283 …__IO uint8_t EMI_0_EC_HOST_IRQ_SELECT; /*!< (@ 0x400F37B8) EMI 0 (EC-to-Host Interrupt) S…
4287 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4296 …__IO uint8_t EMI_1_HOST_IRQ_SELECT; /*!< (@ 0x400F37B9) EMI 1 (Host Event Interrupt) S…
4300 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4309 …__IO uint8_t EMI_1_EC_HOST_IRQ_SELECT; /*!< (@ 0x400F37BA) EMI 1 (EC-to-Host Interrupt) S…
4313 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4322 …__IO uint8_t EMI_2_HOST_IRQ_SELECT; /*!< (@ 0x400F37BB) EMI 2 (Host Event Interrupt) S…
4326 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4335 …__IO uint8_t EMI_2_EC_HOST_IRQ_SELECT; /*!< (@ 0x400F37BC) EMI 2 (EC-to-Host Interrupt) S…
4339 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4348 …__IO uint8_t RTC_IRQ_SELECT; /*!< (@ 0x400F37BD) RTC (RTC Interrupt) Selection …
4351 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4360 …__IO uint8_t EC_IRQ_SELECT; /*!< (@ 0x400F37BE) EC (EC_IRQ Interrupt) Selectio…
4363 …__IO uint8_t IRQ : 8; /*!< [0..7] FFh= IRQ generation from this device is …
4373 …__IO uint8_t ESPI_VWIRE_ERRORS; /*!< (@ 0x400F37F0) eSPI Virtual Wire Errors Regis…
4417 …__IO uint32_t MBX_MEM_BASE_ADDRESS; /*!< (@ 0x400F3930) Mailbox Memory Base Address …
4432 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
4441 …__IO uint16_t ACPI_EC_0_MEM_BASE_ADDRESS_LSB; /*!< (@ 0x400F393A) ACPI EC Channel 0 Memory BAR (…
4459 …__IO uint16_t ACPI_EC_0_MEM_BASE_ADDRESS_MSB; /*!< (@ 0x400F393C) ACPI EC Channel 0 Memory BAR (…
4462 …__IO uint16_t VIRTUALIZED: 1; /*!< [0..0] 1=Peripheral Channel I/O for this device…
4471 …__IO uint32_t ACPI_EC_1_MEM_BASE_ADDRESS; /*!< (@ 0x400F3944) ACPI EC Channel 1 Memory BAR …
4486 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
4495 …__IO uint16_t ACPI_EC_2_MEM_BASE_ADDRESS_LSB; /*!< (@ 0x400F394E) ACPI EC Channel 2 Memory BAR (…
4513 …__IO uint16_t ACPI_EC_2_MEM_BASE_ADDRESS_MSB; /*!< (@ 0x400F3950) ACPI EC Channel 2 Memory BAR (…
4516 …__IO uint16_t VIRTUALIZED: 1; /*!< [0..0] 1=Peripheral Channel I/O for this device…
4525 …__IO uint32_t ACPI_EC_3_MEM_BASE_ADDRESS; /*!< (@ 0x400F3958) ACPI EC Channel 3 Memory BAR …
4540 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
4549 …__IO uint16_t ACPI_EC_4_MEM_BASE_ADDRESS_LSB; /*!< (@ 0x400F3962) ACPI EC Channel 4 Memory BAR (…
4567 …__IO uint16_t ACPI_EC_4_MEM_BASE_ADDRESS_MSB; /*!< (@ 0x400F3964) ACPI EC Channel 4 Memory BAR (…
4570 …__IO uint16_t VIRTUALIZED: 1; /*!< [0..0] 1=Peripheral Channel I/O for this device…
4579 …__IO uint32_t EMI_0_MEM_BASE_ADDRESS; /*!< (@ 0x400F396C) Embedded Memory Interface (EMI…
4595 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
4604 …__IO uint16_t EMI_1_MEM_BASE_ADDRESS_LSB; /*!< (@ 0x400F3976) Embedded Memory Interface (EMI…
4623 …__IO uint16_t EMI_1_MEM_BASE_ADDRESS_MSB; /*!< (@ 0x400F3978) Embedded Memory Interface (EMI…
4627 …__IO uint16_t VIRTUALIZED: 1; /*!< [0..0] 1=Peripheral Channel I/O for this device…
4636 …__IO uint32_t EMI_2_MEM_BASE_ADDRESS; /*!< (@ 0x400F3980) Embedded Memory Interface (EMI…
4652 …__IO uint32_t VIRTUALIZED: 1; /*!< [16..16] 1=Peripheral Channel I/O for this devi…
4661 …__IO uint16_t SRAM_0_MEM_BASE_ADDRESS_CONF; /*!< (@ 0x400F39AC) SRAM 0 Memory Base Address Con…
4664 …__IO uint16_t RAM_VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4666 …__IO uint16_t RAM_ACCESS : 2; /*!< [1..2] These 2 bits define the access type of a…
4673 …__IO uint16_t RAM_SIZE : 4; /*!< [4..7] This field defines the size of the regio…
4685 …__IO uint16_t SRAM_0_MEM_BASE_ADDRESS_LSB; /*!< (@ 0x400F39AE) SRAM 0 Memory Base Address LSB…
4688 …__IO uint16_t RAM_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32-bit field tha…
4696 …__IO uint32_t SRAM_0_MEM_BASE_ADDRESS_MSB; /*!< (@ 0x400F39B0) SRAM 0 Memory Base Address MSB…
4699 …__IO uint32_t RAM_ADDRESS: 16; /*!< [0..15] This is the MSB of the 32-bit field tha…
4708 …__IO uint16_t SRAM_1_MEM_BASE_ADDRESS_CONF; /*!< (@ 0x400F39B6) SRAM 1 Memory Base Address Con…
4711 …__IO uint16_t RAM_VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
4713 …__IO uint16_t RAM_ACCESS : 2; /*!< [1..2] These 2 bits define the access type of a…
4720 …__IO uint16_t RAM_SIZE : 4; /*!< [4..7] This field defines the size of the regio…
4732 …__IO uint16_t SRAM_1_MEM_BASE_ADDRESS_LSB; /*!< (@ 0x400F39B8) SRAM 1 Memory Base Address LSB…
4735 …__IO uint16_t RAM_ADDRESS: 16; /*!< [0..15] This is the LSB of the 32-bit field tha…
4743 …__IO uint16_t SRAM_1_MEM_BASE_ADDRESS_MSB; /*!< (@ 0x400F39BA) SRAM 1 Memory Base Address MSB…
4746 …__IO uint16_t RAM_ADDRESS: 16; /*!< [0..15] This the MSB of the 32-bit field that d…
4755 …__IO uint32_t BUS_MASTER_STATUS; /*!< (@ 0x400F3A00) Bus Master Status Register …
4758 …__IO uint32_t BM1_TRANSFER_DONE: 1; /*!< [0..0] This bit is set to '1' when a START tran…
4776 …__IO uint32_t BM1_ABORTED_BY_EC: 1; /*!< [2..2] This bit is set when the control bit BM1…
4780 …__IO uint32_t BM1_ABORTED_BY_HOST: 1; /*!< [3..3] A '1' in this bit indicates that the las…
4786 …__IO uint32_t BM1_ABORTED_BY_CH2_ERROR: 1; /*!< [4..4] This bit is set if an error occurs on Bu…
4793 …__IO uint32_t BM1_START_OVERFLOW: 1; /*!< [5..5] This bit is set if the bit BM1_START in …
4798 …__IO uint32_t BM1_DATA_OVERRUN: 1; /*!< [6..6] This bit is set if the transfer on Bus M…
4802 …__IO uint32_t BM1_INCOMPLETE: 1; /*!< [7..7] This bit is set if the transfer on Bus M…
4806 …__IO uint32_t BM1_FAIL : 1; /*!< [8..8] This bit is set if a Layer 3 transaction…
4814 …__IO uint32_t BM1_INTERNAL_BUS_ERROR: 1; /*!< [9..9] This bit is set if a transfer on Bus Mas…
4820 …__IO uint32_t BM1_BAD_REQUEST: 1; /*!< [11..11] This bit is set, and the START request…
4833 …__IO uint32_t BM2_TRANSFER_DONE: 1; /*!< [16..16] This bit is set to '1' when a START tr…
4850 …__IO uint32_t BM2_ABORTED_BY_EC: 1; /*!< [18..18] This bit is set when the control bit B…
4853 …__IO uint32_t BM2_ABORTED_BY_HOST: 1; /*!< [19..19] A '1' in this bit indicates that the l…
4860 …__IO uint32_t BM2_ABORTED_BY_CH1_ERROR: 1; /*!< [20..20] This bit is set if an error occurs on …
4867 …__IO uint32_t BM2_START_OVERFLOW: 1; /*!< [21..21] This bit is set if the bit BM2_START i…
4872 …__IO uint32_t BM2_DATA_OVERRUN: 1; /*!< [22..22] This bit is set if the transfer on Bus…
4876 …__IO uint32_t BM2_INCOMPLETE: 1; /*!< [23..23] This bit is set if the transfer on Bus…
4880 …__IO uint32_t BM2_FAIL : 1; /*!< [24..24] This bit is set if a Layer 3 transacti…
4889 …__IO uint32_t BM2_INTERNAL_BUS_ERROR: 1; /*!< [25..25] This bit is set if a transfer on Bus M…
4895 …__IO uint32_t BM2_BAD_REQUEST: 1; /*!< [27..27] This bit is set, and the START request…
4909 …__IO uint32_t BUS_MASTER_INT_EN; /*!< (@ 0x400F3A04) Bus Master Interrupt Enable Re…
4912 …__IO uint32_t BM1_TRANSFER_DONE_EN: 1; /*!< [0..0] When this bit is '1' an interrupt is gen…
4916 …__IO uint32_t BM2_TRANSFER_DONE_EN: 1; /*!< [1..1] When this bit is '1' an interrupt is gen…
4924 …__IO uint32_t BUS_MASTER_CONFIG; /*!< (@ 0x400F3A08) Bus Master Configuration Regis…
4927 …__IO uint32_t BM1_TAG : 4; /*!< [0..3] This 4-bit Tag value is included in all …
4932 …__IO uint32_t BM2_TAG : 4; /*!< [16..19] This 4-bit Tag value is included in al…
4941 …__IO uint32_t BUS_MASTER_1_CONTROL; /*!< (@ 0x400F3A10) Bus Master 1 Control Register …
4957 …__IO uint32_t BM1_ENABLE_INTERNAL_INCR: 1; /*!< [2..2] 1=The internal address will be increment…
4964 …__IO uint32_t BM1_WAIT_BM2_NOT_BUSY: 1; /*!< [3..3] 1=The transfer on Bus Master Channel 1 w…
4972 …__IO uint32_t BM1_CYCLE_TYPE: 2; /*!< [8..9] This field provides the cycle type to us…
4979 …__IO uint32_t BM1_LENGTH : 13; /*!< [16..28] This field sets the length in bytes of…
4993 …__IO uint32_t BUS_MASTER_1_HOST_ADDR_DW0; /*!< (@ 0x400F3A14) Bus Master 1 Host Address Regi…
4997 …__IO uint32_t BM1_HOST_ADDRESS_LSDW: 32; /*!< [0..31] This register sets bits [31:0] of the H…
5007 …__IO uint32_t BUS_MASTER_1_HOST_ADDR_DW1; /*!< (@ 0x400F3A18) Bus Master 1 Host Address Regi…
5011 …__IO uint32_t BM1_HOST_ADDRESS_MSDW: 32; /*!< [0..31] This register sets bits [63:32] of the …
5021 …__IO uint32_t BUS_MASTER_1_INTERNAL_ADDR; /*!< (@ 0x400F3A1C) Bus Master 1 Internal Address …
5025 …__IO uint32_t BM1_INTERNAL_ADDRESS: 30; /*!< [2..31] This register sets the internal address…
5032 …__IO uint32_t BUS_MASTER_2_CONTROL; /*!< (@ 0x400F3A24) Bus Master 2 Control Register …
5048 …__IO uint32_t BM2_ENABLE_INTERNAL_INCR: 1; /*!< [2..2] 1=The internal address will be increment…
5055 …__IO uint32_t BM2_WAIT_BM1_NOT_BUSY: 1; /*!< [3..3] 1=The transfer on Bus Master Channel 2 w…
5063 …__IO uint32_t BM2_CYCLE_TYPE: 2; /*!< [8..9] This field provides the cycle type to us…
5070 …__IO uint32_t BM2_LENGTH : 13; /*!< [16..28] This field sets the length in bytes of…
5084 …__IO uint32_t BUS_MASTER_2_HOST_ADDR_DW0; /*!< (@ 0x400F3A28) Bus Master 2 Host Address Regi…
5088 …__IO uint32_t BM2_HOST_ADDRESS_LSDW: 32; /*!< [0..31] This register sets bits [31:0] of the H…
5098 …__IO uint32_t BUS_MASTER_2_HOST_ADDR_DW1; /*!< (@ 0x400F3A2C) Bus Master 2 Host Address Regi…
5102 …__IO uint32_t BM2_HOST_ADDRESS_MSDW: 32; /*!< [0..31] This register sets bits [63:32] of the …
5112 …__IO uint32_t BUS_MASTER_2_INTERNAL_ADDR; /*!< (@ 0x400F3A30) Bus Master 2 Internal Address …
5116 …__IO uint32_t BM2_INTERNAL_ADDRESS: 30; /*!< [2..31] This register sets the internal address…
5123 …__IO uint16_t MBX_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B30) Mailbox Memory BAR Configurati…
5127 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5133 …__IO uint16_t MBX_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B32) Mailbox Memory BAR Configurati…
5137 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5143 …__IO uint16_t MBX_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B34) Mailbox Memory BAR Configurati…
5147 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5153 …__IO uint16_t MBX_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B36) Mailbox Memory BAR Configurati…
5157 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5163 …__IO uint16_t MBX_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B38) Mailbox Memory BAR Configurati…
5167 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5173 …__IO uint16_t ACPI_EC_0_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B3A) ACPI EC Channel 0 Memory BAR C…
5177 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5183 …__IO uint16_t ACPI_EC_0_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B3C) ACPI EC Channel 0 Memory BAR C…
5187 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5193 …__IO uint16_t ACPI_EC_0_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B3E) ACPI EC Channel 0 Memory BAR C…
5197 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5203 …__IO uint16_t ACPI_EC_0_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B40) ACPI EC Channel 0 Memory BAR C…
5207 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5213 …__IO uint16_t ACPI_EC_0_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B42) ACPI EC Channel 0 Memory BAR C…
5217 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5223 …__IO uint16_t ACPI_EC_1_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B44) ACPI EC Channel 1 Memory BAR C…
5227 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5233 …__IO uint16_t ACPI_EC_1_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B46) ACPI EC Channel 1 Memory BAR C…
5237 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5243 …__IO uint16_t ACPI_EC_1_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B48) ACPI EC Channel 1 Memory BAR C…
5247 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5253 …__IO uint16_t ACPI_EC_1_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B4A) ACPI EC Channel 1 Memory BAR C…
5257 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5263 …__IO uint16_t ACPI_EC_1_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B4C) ACPI EC Channel 1 Memory BAR C…
5267 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5273 …__IO uint16_t ACPI_EC_2_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B4E) ACPI EC Channel 2 Memory BAR C…
5277 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5283 …__IO uint16_t ACPI_EC_2_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B50) ACPI EC Channel 2 Memory BAR C…
5287 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5293 …__IO uint16_t ACPI_EC_2_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B52) ACPI EC Channel 2 Memory BAR C…
5297 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5303 …__IO uint16_t ACPI_EC_2_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B54) ACPI EC Channel 2 Memory BAR C…
5307 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5313 …__IO uint16_t ACPI_EC_2_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B56) ACPI EC Channel 2 Memory BAR C…
5317 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5323 …__IO uint16_t ACPI_EC_3_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B58) ACPI EC Channel 3 Memory BAR C…
5327 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5333 …__IO uint16_t ACPI_EC_3_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B5A) ACPI EC Channel 3 Memory BAR C…
5337 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5343 …__IO uint16_t ACPI_EC_3_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B5C) ACPI EC Channel 3 Memory BAR C…
5347 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5353 …__IO uint16_t ACPI_EC_3_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B5E) ACPI EC Channel 3 Memory BAR C…
5357 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5363 …__IO uint16_t ACPI_EC_3_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B60) ACPI EC Channel 3 Memory BAR C…
5367 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5374 …__IO uint16_t ACPI_EC_4_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B64) ACPI EC Channel 4 Memory BAR C…
5378 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5384 …__IO uint16_t ACPI_EC_4_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B66) ACPI EC Channel 4 Memory BAR C…
5388 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5394 …__IO uint16_t ACPI_EC_4_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B68) ACPI EC Channel 4 Memory BAR C…
5398 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5404 …__IO uint16_t ACPI_EC_4_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B6A) ACPI EC Channel 4 Memory BAR C…
5408 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5414 …__IO uint16_t EMI_0_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B6C) EMI 0 Memory BAR Configuration…
5418 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5424 …__IO uint16_t EMI_0_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B6E) EMI 0 Memory BAR Configuration…
5428 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5434 …__IO uint16_t EMI_0_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B70) EMI 0 Memory BAR Configuration…
5438 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5444 …__IO uint16_t EMI_0_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B72) EMI 0 Memory BAR Configuration…
5448 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5454 …__IO uint16_t EMI_0_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B74) EMI 0 Memory BAR Configuration…
5458 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5464 …__IO uint16_t EMI_1_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B76) EMI 1 Memory BAR Configuration…
5468 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5474 …__IO uint16_t EMI_1_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B78) EMI 1 Memory BAR Configuration…
5478 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5484 …__IO uint16_t EMI_1_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B7A) EMI 1 Memory BAR Configuration…
5488 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5494 …__IO uint16_t EMI_1_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B7C) EMI 1 Memory BAR Configuration…
5498 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5504 …__IO uint16_t EMI_1_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B7E) EMI 1 Memory BAR Configuration…
5508 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5514 …__IO uint16_t EMI_2_MEM_BAR_CFG_W0; /*!< (@ 0x400F3B80) EMI 2 Memory BAR Configuration…
5518 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5524 …__IO uint16_t EMI_2_MEM_BAR_CFG_W1; /*!< (@ 0x400F3B82) EMI 2 Memory BAR Configuration…
5528 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5534 …__IO uint16_t EMI_2_MEM_BAR_CFG_W2; /*!< (@ 0x400F3B84) EMI 2 Memory BAR Configuration…
5538 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5544 …__IO uint16_t EMI_2_MEM_BAR_CFG_W3; /*!< (@ 0x400F3B86) EMI 2 Memory BAR Configuration…
5548 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5554 …__IO uint16_t EMI_2_MEM_BAR_CFG_W4; /*!< (@ 0x400F3B88) EMI 2 Memory BAR Configuration…
5558 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5565 …__IO uint16_t SRAM_0_MEM_BAR_CFG_W0; /*!< (@ 0x400F3BAC) SRAM BAR 0 Configuration Regis…
5568 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5574 …__IO uint16_t SRAM_0_MEM_BAR_CFG_W1; /*!< (@ 0x400F3BAE) SRAM BAR 0 Configuration Regis…
5577 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5583 …__IO uint16_t SRAM_0_MEM_BAR_CFG_W2; /*!< (@ 0x400F3BB0) SRAM BAR 0 Configuration Regis…
5586 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5592 …__IO uint16_t SRAM_0_MEM_BAR_CFG_W3; /*!< (@ 0x400F3BB2) SRAM BAR 0 Configuration Regis…
5595 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5601 …__IO uint16_t SRAM_0_MEM_BAR_CFG_W4; /*!< (@ 0x400F3BB4) SRAM BAR 0 Configuration Regis…
5604 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5610 …__IO uint16_t SRAM_1_MEM_BAR_CFG_W0; /*!< (@ 0x400F3BB6) SRAM BAR 1 Configuration Regis…
5613 …__IO uint16_t VALID : 1; /*!< [0..0] 1=The BAR is valid and will participate …
5619 …__IO uint16_t SRAM_1_MEM_BAR_CFG_W1; /*!< (@ 0x400F3BB8) SRAM BAR 1 Configuration Regis…
5622 …__IO uint16_t ESPI_HOST_ADDRESS_W0: 16; /*!< [0..15] Bits[15:0] of the 64 bits that are used…
5628 …__IO uint16_t SRAM_1_MEM_BAR_CFG_W2; /*!< (@ 0x400F3BBA) SRAM BAR 1 Configuration Regis…
5631 …__IO uint16_t ESPI_HOST_ADDRESS_W1: 16; /*!< [0..15] Bits[31:16] of the 64 bits that are use…
5637 …__IO uint16_t SRAM_1_MEM_BAR_CFG_W3; /*!< (@ 0x400F3BBC) SRAM BAR 1 Configuration Regis…
5640 …__IO uint16_t ESPI_HOST_ADDRESS_W2: 16; /*!< [0..15] Bits[47:32] of the 64 bits that are use…
5646 …__IO uint16_t SRAM_1_MEM_BAR_CFG_W4; /*!< (@ 0x400F3BBE) SRAM BAR 1 Configuration Regis…
5649 …__IO uint16_t ESPI_HOST_ADDRESS_W3: 16; /*!< [0..15] Bits[63:48] of the 64 bits that are use…
5668 …__IO uint32_t MSVW00_DW0; /*!< (@ 0x400F9C00) Master-to-Slave Virtual Wire 0…
5672 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
5682 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
5690 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
5701 …__IO uint32_t MSVW00_DW1; /*!< (@ 0x400F9C04) Master-to-Slave Virtual Wire 0…
5705 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
5710 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
5715 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
5720 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
5728 …__IO uint32_t MSVW00_DW2; /*!< (@ 0x400F9C08) Master-to-Slave Virtual Wire 0…
5732 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
5735 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
5738 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
5741 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
5747 …__IO uint32_t MSVW01_DW0; /*!< (@ 0x400F9C0C) Master-to-Slave Virtual Wire 1…
5751 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
5761 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
5769 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
5780 …__IO uint32_t MSVW01_DW1; /*!< (@ 0x400F9C10) Master-to-Slave Virtual Wire 1…
5784 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
5789 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
5794 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
5799 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
5807 …__IO uint32_t MSVW01_DW2; /*!< (@ 0x400F9C14) Master-to-Slave Virtual Wire 1…
5811 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
5814 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
5817 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
5820 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
5826 …__IO uint32_t MSVW02_DW0; /*!< (@ 0x400F9C18) Master-to-Slave Virtual Wire 2…
5830 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
5840 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
5848 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
5859 …__IO uint32_t MSVW02_DW1; /*!< (@ 0x400F9C1C) Master-to-Slave Virtual Wire 2…
5863 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
5868 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
5873 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
5878 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
5886 …__IO uint32_t MSVW02_DW2; /*!< (@ 0x400F9C20) Master-to-Slave Virtual Wire 2…
5890 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
5893 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
5896 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
5899 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
5905 …__IO uint32_t MSVW03_DW0; /*!< (@ 0x400F9C24) Master-to-Slave Virtual Wire 3…
5909 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
5919 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
5927 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
5938 …__IO uint32_t MSVW03_DW1; /*!< (@ 0x400F9C28) Master-to-Slave Virtual Wire 3…
5942 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
5947 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
5952 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
5957 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
5965 …__IO uint32_t MSVW03_DW2; /*!< (@ 0x400F9C2C) Master-to-Slave Virtual Wire 3…
5969 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
5972 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
5975 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
5978 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
5984 …__IO uint32_t MSVW04_DW0; /*!< (@ 0x400F9C30) Master-to-Slave Virtual Wire 4…
5988 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
5998 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6006 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6017 …__IO uint32_t MSVW04_DW1; /*!< (@ 0x400F9C34) Master-to-Slave Virtual Wire 4…
6021 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6026 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6031 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6036 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6044 …__IO uint32_t MSVW04_DW2; /*!< (@ 0x400F9C38) Master-to-Slave Virtual Wire 4…
6048 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6051 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6054 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6057 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6063 …__IO uint32_t MSVW05_DW0; /*!< (@ 0x400F9C3C) Master-to-Slave Virtual Wire 5…
6067 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6077 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6085 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6096 …__IO uint32_t MSVW05_DW1; /*!< (@ 0x400F9C40) Master-to-Slave Virtual Wire 5…
6100 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6105 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6110 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6115 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6123 …__IO uint32_t MSVW05_DW2; /*!< (@ 0x400F9C44) Master-to-Slave Virtual Wire 5…
6127 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6130 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6133 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6136 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6142 …__IO uint32_t MSVW06_DW0; /*!< (@ 0x400F9C48) Master-to-Slave Virtual Wire 6…
6146 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6156 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6164 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6175 …__IO uint32_t MSVW06_DW1; /*!< (@ 0x400F9C4C) Master-to-Slave Virtual Wire 6…
6179 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6184 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6189 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6194 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6202 …__IO uint32_t MSVW06_DW2; /*!< (@ 0x400F9C50) Master-to-Slave Virtual Wire 6…
6206 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6209 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6212 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6215 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6234 …__IO uint32_t MSVW07_DW0; /*!< (@ 0x400F9C54) Master-to-Slave Virtual Wire 7…
6238 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6248 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6256 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6267 …__IO uint32_t MSVW07_DW1; /*!< (@ 0x400F9C58) Master-to-Slave Virtual Wire 7…
6271 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6276 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6281 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6286 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6294 …__IO uint32_t MSVW07_DW2; /*!< (@ 0x400F9C5C) Master-to-Slave Virtual Wire 7…
6298 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6301 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6304 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6307 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6313 …__IO uint32_t MSVW08_DW0; /*!< (@ 0x400F9C60) Master-to-Slave Virtual Wire 8…
6317 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6327 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6335 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6346 …__IO uint32_t MSVW08_DW1; /*!< (@ 0x400F9C64) Master-to-Slave Virtual Wire 8…
6350 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6355 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6360 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6365 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6373 …__IO uint32_t MSVW08_DW2; /*!< (@ 0x400F9C68) Master-to-Slave Virtual Wire 8…
6377 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6380 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6383 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6386 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6392 …__IO uint32_t MSVW09_DW0; /*!< (@ 0x400F9C6C) Master-to-Slave Virtual Wire 9…
6396 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6406 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6414 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6425 …__IO uint32_t MSVW09_DW1; /*!< (@ 0x400F9C70) Master-to-Slave Virtual Wire 9…
6429 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6434 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6439 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6444 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6452 …__IO uint32_t MSVW09_DW2; /*!< (@ 0x400F9C74) Master-to-Slave Virtual Wire 9…
6456 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6459 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6462 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6465 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6471 …__IO uint32_t MSVW10_DW0; /*!< (@ 0x400F9C78) Master-to-Slave Virtual Wire 1…
6475 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6485 …__IO uint32_t MTOS_SRC : 2; /*!< [8..9] This field determines which reset signal…
6493 …__IO uint32_t MTOS_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6504 …__IO uint32_t MSVW10_DW1; /*!< (@ 0x400F9C7C) Master-to-Slave Virtual Wire 1…
6508 …__IO uint32_t SRC0_IRQ_SELECT: 4; /*!< [0..3] A change in the value of SRC0 will gener…
6513 …__IO uint32_t SRC1_IRQ_SELECT: 4; /*!< [8..11] A change in the value of SRC1 will gene…
6518 …__IO uint32_t SRC2_IRQ_SELECT: 4; /*!< [16..19] A change in the value of SRC2 will gen…
6523 …__IO uint32_t SRC3_IRQ_SELECT: 4; /*!< [24..27] A change in the value of SRC3 will gen…
6531 …__IO uint32_t MSVW10_DW2; /*!< (@ 0x400F9C80) Master-to-Slave Virtual Wire 1…
6535 …__IO uint32_t SRC0 : 1; /*!< [0..0] Master-to-Slave data for Bit Position 0 …
6538 …__IO uint32_t SRC1 : 1; /*!< [8..8] Master-to-Slave data for Bit Position 1 …
6541 …__IO uint32_t SRC2 : 1; /*!< [16..16] Master-to-Slave data for Bit Position …
6544 …__IO uint32_t SRC3 : 1; /*!< [24..24] Master-to-Slave data for Bit Position …
6563 …__IO uint32_t SMVW00_DW0; /*!< (@ 0x400F9E00) Slave-to-Master Virtual Wire 0…
6567 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6575 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
6583 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6626 …__IO uint32_t SMVW00_DW1; /*!< (@ 0x400F9E04) Slave-to-Master Virtual Wire 0…
6630 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
6637 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
6644 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
6651 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
6661 …__IO uint32_t SMVW01_DW0; /*!< (@ 0x400F9E08) Slave-to-Master Virtual Wire 1…
6665 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6673 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
6681 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6724 …__IO uint32_t SMVW01_DW1; /*!< (@ 0x400F9E0C) Slave-to-Master Virtual Wire 1…
6728 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
6735 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
6742 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
6749 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
6759 …__IO uint32_t SMVW02_DW0; /*!< (@ 0x400F9E10) Slave-to-Master Virtual Wire 2…
6763 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6771 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
6779 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6822 …__IO uint32_t SMVW02_DW1; /*!< (@ 0x400F9E14) Slave-to-Master Virtual Wire 2…
6826 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
6833 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
6840 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
6847 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
6857 …__IO uint32_t SMVW03_DW0; /*!< (@ 0x400F9E18) Slave-to-Master Virtual Wire 3…
6861 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6869 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
6877 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
6920 …__IO uint32_t SMVW03_DW1; /*!< (@ 0x400F9E1C) Slave-to-Master Virtual Wire 3…
6924 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
6931 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
6938 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
6945 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
6955 …__IO uint32_t SMVW04_DW0; /*!< (@ 0x400F9E20) Slave-to-Master Virtual Wire 4…
6959 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
6967 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
6975 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7018 …__IO uint32_t SMVW04_DW1; /*!< (@ 0x400F9E24) Slave-to-Master Virtual Wire 4…
7022 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7029 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7036 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7043 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7053 …__IO uint32_t SMVW05_DW0; /*!< (@ 0x400F9E28) Slave-to-Master Virtual Wire 5…
7057 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
7065 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
7073 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7116 …__IO uint32_t SMVW05_DW1; /*!< (@ 0x400F9E2C) Slave-to-Master Virtual Wire 5…
7120 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7127 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7134 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7141 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7151 …__IO uint32_t SMVW06_DW0; /*!< (@ 0x400F9E30) Slave-to-Master Virtual Wire 6…
7155 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
7163 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
7171 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7214 …__IO uint32_t SMVW06_DW1; /*!< (@ 0x400F9E34) Slave-to-Master Virtual Wire 6…
7218 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7225 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7232 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7239 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7249 …__IO uint32_t SMVW07_DW0; /*!< (@ 0x400F9E38) Slave-to-Master Virtual Wire 7…
7253 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
7261 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
7269 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7312 …__IO uint32_t SMVW07_DW1; /*!< (@ 0x400F9E3C) Slave-to-Master Virtual Wire 7…
7316 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7323 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7330 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7337 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7347 …__IO uint32_t SMVW08_DW0; /*!< (@ 0x400F9E40) Slave-to-Master Virtual Wire 8…
7351 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
7359 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
7367 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7410 …__IO uint32_t SMVW08_DW1; /*!< (@ 0x400F9E44) Slave-to-Master Virtual Wire 8…
7414 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7421 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7428 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7435 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7445 …__IO uint32_t SMVW09_DW0; /*!< (@ 0x400F9E48) Slave-to-Master Virtual Wire 9…
7449 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
7457 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
7465 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7508 …__IO uint32_t SMVW09_DW1; /*!< (@ 0x400F9E4C) Slave-to-Master Virtual Wire 9…
7512 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7519 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7526 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7533 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7543 …__IO uint32_t SMVW10_DW0; /*!< (@ 0x400F9E50) Slave-to-Master Virtual Wire 1…
7547 …__IO uint32_t INDEX : 8; /*!< [0..7] The Index for SRC0, SRC1, SRC2 and SRC3.…
7555 …__IO uint32_t STOM_SRC : 2; /*!< [8..9] This field determines which reset signal…
7563 …__IO uint32_t STOM_R_STATE: 4; /*!< [12..15] The four bits in this field are loaded…
7606 …__IO uint32_t SMVW10_DW1; /*!< (@ 0x400F9E54) Slave-to-Master Virtual Wire 1…
7610 …__IO uint32_t SRC0 : 1; /*!< [0..0] Slave-to-Master data for Bit Position 0 …
7617 …__IO uint32_t SRC1 : 1; /*!< [8..8] Slave-to-Master data for Bit Position 1 …
7624 …__IO uint32_t SRC2 : 1; /*!< [16..16] Slave-to-Master data for Bit Position …
7631 …__IO uint32_t SRC3 : 1; /*!< [24..24] Slave-to-Master data for Bit Position …
7655 …__IO uint8_t LOGICAL_DEVICE_NUMBER; /*!< (@ 0x400FFF07) A write to this register sel…
7733 …__IO uint8_t EC_KBD_STATUS; /*!< (@ 0x400F0504) Keyboard Status Register …
7738 …__IO uint8_t UD0 : 1; /*!< [2..2] User-defined data. …
7742 …__IO uint8_t UD1 : 1; /*!< [4..4] User-defined data. …
7744 …__IO uint8_t UD2 : 2; /*!< [6..7] User-defined data. …
7750 …__IO uint8_t CONTROL; /*!< (@ 0x400F0508) Keyboard Control Register …
7753 …__IO uint8_t UD3 : 1; /*!< [0..0] User-defined data. …
7754 …__IO uint8_t SAEN : 1; /*!< [1..1] Software-assist enable. 1=This bit allow…
7759 …__IO uint8_t PCOBFEN : 1; /*!< [2..2] 1= reflects the value written to the PCO…
7762 …__IO uint8_t UD4 : 2; /*!< [3..4] User-defined data. …
7763 …__IO uint8_t OBFEN : 1; /*!< [5..5] When this bit is '1', the system interru…
7769 …__IO uint8_t UD5 : 1; /*!< [6..6] User-defined data. …
7770 …__IO uint8_t AUXH : 1; /*!< [7..7] AUX in Hardware. 1=AUXOBF of the Keyboar…
7788 …__IO uint8_t PCOBF; /*!< (@ 0x400F0514) 8042 Emulated Keyboard Control…
7792 …__IO uint8_t PCOBF : 1; /*!< [0..0] PCOBF Register: If enabled by the bit OB…
7801 …__IO uint8_t ACTIVATE; /*!< (@ 0x400F0730) Activate Register …
7804 …__IO uint8_t ACTIVATE : 1; /*!< [0..0] 1=The 8042 Interface is powered and func…
7823 …__IO uint8_t PORT92_REG; /*!< (@ 0x400F2000) PORT92 Register: The registers…
7828 …__IO uint8_t ALT_CPU_RESET: 1; /*!< [0..0] This bit provides an alternate means to …
7830 …__IO uint8_t ALT_GATE_A20: 1; /*!< [1..1] This bit provides an alternate means for…
7842 …__IO uint8_t GATEA20; /*!< (@ 0x400F2100) GATEA20 Control Register …
7845 …__IO uint8_t GATEA20 : 1; /*!< [0..0] 0=The GATEA20 output is driven low, 1=Th…
7853 …__IO uint8_t RSTGA20L; /*!< (@ 0x400F210C) RSTGA20L Register. A write t…
7858 …__IO uint8_t PORT92_ENABLE; /*!< (@ 0x400F2330) PORT92 Enable Register …
7861 …__IO uint8_t P92_EN : 1; /*!< [0..0] When this bit is '1', the Port92h Regist…
7883 …__IO uint8_t ACPI_OS_DATA_BYTE_[4]; /*!< (@ 0x400F0800) This is byte n of the 32-bit…
7962 …__IO uint8_t EC2OS_DATA_EC_BYTE_[4]; /*!< (@ 0x400F0900) This is byte n of the 32-bit…
7968 …__IO uint8_t EC_STATUS; /*!< (@ 0x400F0904) EC STATUS …
7977 …__IO uint8_t UD1A : 1; /*!< [2..2] UD1A User Defined …
7981 …__IO uint8_t BURST : 1; /*!< [4..4] The BURST bit is set when the ACPI_EC is…
7983 …__IO uint8_t SCI_EVT : 1; /*!< [5..5] This bit is set by software when an SCI …
7985 …__IO uint8_t SMI_EVT : 1; /*!< [6..6] This bit is set when an SMI event is pen…
7986 …__IO uint8_t UD0A : 1; /*!< [7..7] User Defined …
7991 …__IO uint8_t EC_BYTE_CONTROL; /*!< (@ 0x400F0905) Byte Control EC-Register …
7994 …__IO uint8_t FOUR_BYTE_ACCESS: 1; /*!< [0..0] When this bit is set to '1', the ACPI Em…
8004 …__IO uint8_t OS2EC_DATA_EC_BYTE_[4]; /*!< (@ 0x400F0908) OS_TO_EC_DATA_BYTE_n. This i…
8027 …__IO uint8_t PM1_STS2; /*!< (@ 0x400F1C01) PM1 Status 2 …
8030 …__IO uint8_t PWRBTN_STS : 1; /*!< [0..0] This bit can be set or cleared by the EC…
8035 …__IO uint8_t SLPBTN_STS : 1; /*!< [1..1] This bit can be set or cleared by the EC…
8041 …__IO uint8_t RTC_STS : 1; /*!< [2..2] This bit can be set or cleared by the EC…
8045 …__IO uint8_t PWRBTNOR_STS: 1; /*!< [3..3] This bit can be set or cleared by the EC…
8052 …__IO uint8_t WAK_STS : 1; /*!< [7..7] This bit can be set or cleared by the EC…
8059 …__IO uint8_t PM1_EN2; /*!< (@ 0x400F1C03) PM1 Enable 2 …
8062 …__IO uint8_t PWRBTN_EN : 1; /*!< [0..0] This bit can be read or written by the H…
8064 …__IO uint8_t SLPBTN_EN : 1; /*!< [1..1] This bit can be read or written by the H…
8066 …__IO uint8_t RTC_EN : 1; /*!< [2..2] This bit can be read or written by the H…
8073 …__IO uint8_t PM1_CTRL2; /*!< (@ 0x400F1C05) PM1 Control 2 …
8077 …__IO uint8_t PWRBTNOR_EN: 1; /*!< [1..1] This bit can be set or cleared by the Ho…
8079 …__IO uint8_t SLP_TYP : 3; /*!< [2..4] These bits can be set or cleared by the …
8081 …__IO uint8_t SLP_EN : 1; /*!< [5..5] SLP_EN …
8087 …__IO uint8_t PM1_STS_2; /*!< (@ 0x400F1D01) PM1 Status 2 …
8090 …__IO uint8_t PWRBTN_STS : 1; /*!< [0..0] This bit can be set or cleared by the EC…
8095 …__IO uint8_t SLPBTN_STS : 1; /*!< [1..1] This bit can be set or cleared by the EC…
8101 …__IO uint8_t RTC_STS : 1; /*!< [2..2] This bit can be set or cleared by the EC…
8105 …__IO uint8_t PWRBTNOR_STS: 1; /*!< [3..3] This bit can be set or cleared by the EC…
8112 …__IO uint8_t WAK_STS : 1; /*!< [7..7] This bit can be set or cleared by the EC…
8119 …__IO uint8_t PM1_EN_2; /*!< (@ 0x400F1D03) PM1 Enable 2 …
8122 …__IO uint8_t PWRBTN_EN : 1; /*!< [0..0] This bit can be read or written by the H…
8124 …__IO uint8_t SLPBTN_EN : 1; /*!< [1..1] This bit can be read or written by the H…
8126 …__IO uint8_t RTC_EN : 1; /*!< [2..2] This bit can be read or written by the H…
8133 …__IO uint8_t PM1_CTRL_2; /*!< (@ 0x400F1D05) PM1 Control 2 …
8137 …__IO uint8_t PWRBTNOR_EN: 1; /*!< [1..1] This bit can be set or cleared by the Ho…
8139 …__IO uint8_t SLP_TYP : 3; /*!< [2..4] These bits can be set or cleared by the …
8141 …__IO uint8_t SLP_EN : 1; /*!< [5..5] SLP_EN …
8147 …__IO uint8_t PM_STS; /*!< (@ 0x400F1D10) PM1 EC PM Status …
8150 …__IO uint8_t EC_SCI_STS : 1; /*!< [0..0] If the EC_SCI_STS bit is '1', an interru…
8152 …__IO uint8_t UD : 7; /*!< [1..7] User Defined …
8169 …__IO uint8_t HOST_EC_MBX; /*!< (@ 0x400F4000) Host-to-EC Mailbox Register …
8170 …__IO uint8_t EC_HOST_MBX; /*!< (@ 0x400F4001) EC-to-Host Mailbox Register …
8173 …__IO uint8_t EC_ADDRESS_LSB; /*!< (@ 0x400F4002) EC Address Access Control Regi…
8176 …__IO uint8_t ACCESS_TYPE: 2; /*!< [0..1] This field defines the type of access th…
8180 …__IO uint8_t EC_ADDRESS_LSB: 6; /*!< [2..7] This field defines bits[7:2] of EC_Addre…
8191 …__IO uint8_t EC_ADDRESS_MSB; /*!< (@ 0x400F4003) EC Address Access Control Regi…
8195 …__IO uint8_t EC_ADDRESS_MSB: 5; /*!< [2..6] This field defines bits[14:8] of EC_Addr…
8202 …__IO uint8_t REGION : 1; /*!< [7..7] The field specifies which of two segment…
8212 …__IO uint8_t EC_DATA_BYTE[4]; /*!< (@ 0x400F4004) EC Data Byte Register …
8215 …__IO uint8_t EC_INT_SOURCE_LSB; /*!< (@ 0x400F4008) Interrupt Source LSB Register …
8218 …__IO uint8_t EC_WR : 1; /*!< [0..0] EC Mailbox Write. This bit is set when t…
8222 …__IO uint8_t EC_SWI_LSB : 7; /*!< [1..7] EC Software Interrupt Least Significant …
8235 …__IO uint8_t EC_INT_SOURCE_MSB; /*!< (@ 0x400F4009) Interrupt Source MSB Register …
8238 …__IO uint8_t EC_SWI_MSB : 8; /*!< [0..7] EC Software Interrupt Most Significant B…
8251 …__IO uint8_t EC_INT_MASK_LSB; /*!< (@ 0x400F400A) Interrupt Mask LSB Register …
8254 …__IO uint8_t TEST : 1; /*!< [0..0] Test Bit. …
8255 …__IO uint8_t EC_SWI_EN_LSB: 7; /*!< [1..7] EC Software Interrupt Enable Least Signi…
8263 …__IO uint8_t EC_INT_MASK_MSB; /*!< (@ 0x400F400B) Interrupt Mask MSB Register …
8267 …__IO uint8_t EC_SWI_EN_MSB: 7; /*!< [1..7] EC Software Interrupt Enable Most Signif…
8273 …__IO uint8_t APPLICATION_ID; /*!< (@ 0x400F400C) Application ID Register, APP…
8279 …__IO uint8_t HOST2EC_MBX; /*!< (@ 0x400F4100) Host-to-EC Mailbox Register,…
8283 …__IO uint8_t EC2HOST_MBX; /*!< (@ 0x400F4101) EC-to-Host Mailbox Register,…
8288 …__IO uint32_t MEMORY_BASE_ADDRESS_0; /*!< (@ 0x400F4104) Memory Base Address 0 Regist…
8297 …__IO uint16_t MEMORY_READ_LIMIT_0; /*!< (@ 0x400F4108) Memory Read Limit 0 Register…
8303 …__IO uint16_t MEMORY_WRITE_LIMIT_0; /*!< (@ 0x400F410A) Memory Write Limit 0 Registe…
8312 …__IO uint32_t MEMORY_BASE_ADDRESS_1; /*!< (@ 0x400F410C) Memory Base Address 1 Regist…
8321 …__IO uint16_t MEMORY_READ_LIMIT_1; /*!< (@ 0x400F4110) Memory Read Limit 1 Register…
8327 …__IO uint16_t MEMORY_WRITE_LIMIT_1; /*!< (@ 0x400F4112) Memory Write Limit 1 Registe…
8336 …__IO uint16_t EC_SWI_SET; /*!< (@ 0x400F4114) [15:1] Interrupt Set Registe…
8341 …__IO uint16_t CLEAR_ENABLE; /*!< (@ 0x400F4116) [15:1] Host Clear Enable Reg…
8360 …__IO uint8_t INDEX; /*!< (@ 0x400F0000) MBX_Index Register …
8361 …__IO uint8_t DATA_REG; /*!< (@ 0x400F0001) MBX_Data_Register …
8363 …__IO uint32_t HOST_TO_EC; /*!< (@ 0x400F0100) If enabled, an interrupt to …
8367 …__IO uint8_t EC_TO_HOST; /*!< (@ 0x400F0104) An EC write to this register…
8374 …__IO uint32_t SMI_SOURCE; /*!< (@ 0x400F0108) SMI Interrupt Source Register …
8384 …__IO uint32_t EC_SWI : 7; /*!< [1..7] EC Software Interrupt. An SIRQ to the Ho…
8392 …__IO uint32_t SMI_MASK; /*!< (@ 0x400F010C) SMI Interrupt Mask Register …
8395 …__IO uint32_t EC_WR_EN : 1; /*!< [0..0] EC Mailbox Write.Interrupt Enable. Each …
8400 …__IO uint32_t EC_SWI_EN : 7; /*!< [1..7] EC Software Interrupt Enable. If this bi…
8406 …__IO uint32_t MBX_REG[8]; /*!< (@ 0x400F0110) Mailbox Register …
8423 …__IO uint8_t BAUDRATE_LSB; /*!< (@ 0x400F2400) UART Programmable BAUD Rate Ge…
8433 …__IO uint8_t INT_EN; /*!< (@ 0x400F2401) UART Interrupt Enable Register (…
8436 …__IO uint8_t ERDAI : 1; /*!< [0..0] ERDAI This bit enables the Received Data A…
8439 …__IO uint8_t ETHREI : 1; /*!< [1..1] ETHREI This bit enables the Transmitter Ho…
8441 …__IO uint8_t ELSI : 1; /*!< [2..2] ELSI This bit enables the Received Line St…
8443 …__IO uint8_t EMSI : 1; /*!< [3..3] EMSI This bit enables the MODEM Status Int…
8447 …__IO uint8_t BAUDRATE_MSB; /*!< (@ 0x400F2401) UART Programmable BAUD Rate Ge…
8457 …__IO uint8_t INT_ID; /*!< (@ 0x400F2402) UART Interrupt Identification Re…
8472 …__IO uint8_t FIFO_CR; /*!< (@ 0x400F2402) UART FIFO Control Register …
8483 …__IO uint8_t DMA_MODE_SELECT: 1; /*!< [3..3] DMA_MODE_SELECT Writing to this bit has no…
8487 …__IO uint8_t RECV_FIFO_TRIGGER_LEVEL: 2; /*!< [6..7] RECV_FIFO_TRIGGER_LEVEL These bits are use…
8494 …__IO uint8_t LINE_CR; /*!< (@ 0x400F2403) UART Line Control Register …
8497 …__IO uint8_t WORD_LENGTH: 2; /*!< [0..1] WORD_LENGTH These two bits specify the n…
8499 …__IO uint8_t STOP_BITS : 1; /*!< [2..2] STOP_BITS This bit specifies the number …
8501 …__IO uint8_t ENABLE_PARITY: 1; /*!< [3..3] ENABLE_PARITY Parity Enable bit. …
8502 …__IO uint8_t PARITY_SELECT: 1; /*!< [4..4] PARITY_SELECT Even Parity Select bit. …
8503 …__IO uint8_t STICK_PARITY: 1; /*!< [5..5] STICK_PARITY Stick Parity bit. …
8504 …__IO uint8_t BREAK_CONTROL: 1; /*!< [6..6] BREAK_CONTROL Set Break Control bit …
8505 …__IO uint8_t DLAB : 1; /*!< [7..7] DLAB Divisor Latch Access Bit (DLAB). …
8510 …__IO uint8_t MODEM_CR; /*!< (@ 0x400F2404) UART Modem Control Register …
8513 …__IO uint8_t DTR : 1; /*!< [0..0] DTR This bit controls the Data Terminal …
8515 …__IO uint8_t RTS : 1; /*!< [1..1] RTS This bit controls the Request To Sen…
8517 …__IO uint8_t OUT1 : 1; /*!< [2..2] OUT1 This bit controls the Output 1 (OUT…
8518 …__IO uint8_t OUT2 : 1; /*!< [3..3] OUT2 This bit is used to enable an UART …
8519 …__IO uint8_t LOOPBACK : 1; /*!< [4..4] LOOPBACK This bit provides the loopback …
8553 …__IO uint8_t nCTS : 1; /*!< [4..4] nCTS This bit is the complement of the C…
8555 …__IO uint8_t nDSR : 1; /*!< [5..5] This bit is the complement of the Data S…
8557 …__IO uint8_t nRI : 1; /*!< [6..6] nRI This bit is the complement of the Ri…
8559 …__IO uint8_t nDCD : 1; /*!< [7..7] nDCD This bit is the complement of the D…
8563 …__IO uint8_t SCRATCHPAD; /*!< (@ 0x400F2407) UART Scratchpad Register Thi…
8568 …__IO uint8_t ACTIVATE; /*!< (@ 0x400F2730) UART Activate Register. [0:0…
8575 …__IO uint8_t CONFIG; /*!< (@ 0x400F27F0) UART Config Select Register …
8578 …__IO uint8_t CLK_SRC : 1; /*!< [0..0] CLK_SRC 1=The UART Baud Clock is derived…
8581 …__IO uint8_t POWER : 1; /*!< [1..1] POWER 1=The RESET reset signal is derive…
8583 …__IO uint8_t POLARITY : 1; /*!< [2..2] POLARITY 1=The UART_TX and UART_RX pins …
8603 …__IO uint32_t GPIO_000_PIN_CONTROL; /*!< (@ 0x40081000) GPIO000 Pin Control …
8606 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
8610 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
8614 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
8622 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
8625 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
8634 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
8641 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
8649 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
8659 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
8664 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
8684 …__IO uint32_t GPIO_001_PIN_CONTROL; /*!< (@ 0x40081004) GPIO 001 Pin Control …
8687 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
8691 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
8695 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
8703 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
8706 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
8715 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
8722 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
8730 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
8740 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
8745 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
8765 …__IO uint32_t GPIO_002_PIN_CONTROL; /*!< (@ 0x40081008) GPIO 002 Pin Control …
8768 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
8772 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
8776 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
8784 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
8787 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
8796 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
8803 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
8811 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
8821 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
8826 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
8846 …__IO uint32_t GPIO_003_PIN_CONTROL; /*!< (@ 0x4008100C) GPIO 003 Pin Control …
8849 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
8853 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
8857 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
8865 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
8868 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
8877 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
8884 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
8892 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
8902 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
8907 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
8927 …__IO uint32_t GPIO_004_PIN_CONTROL; /*!< (@ 0x40081010) GPIO 004 Pin Control …
8930 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
8934 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
8938 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
8946 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
8949 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
8958 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
8965 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
8973 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
8983 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
8988 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9008 …__IO uint32_t GPIO_005_PIN_CONTROL; /*!< (@ 0x40081014) GPIO 005 Pin Control …
9011 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9015 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9019 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9027 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9030 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9039 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9046 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9054 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9064 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9069 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9089 …__IO uint32_t GPIO_006_PIN_CONTROL; /*!< (@ 0x40081018) GPIO 006 Pin Control …
9092 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9096 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9100 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9108 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9111 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9120 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9127 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9135 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9145 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9150 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9170 …__IO uint32_t GPIO_007_PIN_CONTROL; /*!< (@ 0x4008101C) GPIO 007 Pin Control …
9173 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9177 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9181 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9189 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9192 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9201 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9208 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9216 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9226 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9231 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9251 …__IO uint32_t GPIO_010_PIN_CONTROL; /*!< (@ 0x40081020) GPIO 010 Pin Control …
9254 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9258 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9262 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9270 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9273 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9282 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9289 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9297 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9307 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9312 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9332 …__IO uint32_t GPIO_011_PIN_CONTROL; /*!< (@ 0x40081024) GPIO 011 Pin Control …
9335 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9339 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9343 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9351 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9354 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9363 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9370 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9378 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9388 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9393 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9413 …__IO uint32_t GPIO_012_PIN_CONTROL; /*!< (@ 0x40081028) GPIO 012 Pin Control …
9416 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9420 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9424 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9432 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9435 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9444 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9451 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9459 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9469 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9474 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9494 …__IO uint32_t GPIO_013_PIN_CONTROL; /*!< (@ 0x4008102C) GPIO 013 Pin Control …
9497 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9501 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9505 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9513 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9516 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9525 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9532 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9540 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9550 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9555 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9575 …__IO uint32_t GPIO_014_PIN_CONTROL; /*!< (@ 0x40081030) GPIO 014 Pin Control …
9578 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9582 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9586 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9594 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9597 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9606 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9613 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9621 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9631 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9636 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9656 …__IO uint32_t GPIO_015_PIN_CONTROL; /*!< (@ 0x40081034) GPIO 015 Pin Control …
9659 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9663 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9667 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9675 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9678 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9687 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9694 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9702 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9712 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9717 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9737 …__IO uint32_t GPIO_016_PIN_CONTROL; /*!< (@ 0x40081038) GPIO 016 Pin Control …
9740 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9744 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9748 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9756 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9759 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9768 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9775 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9783 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9793 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9798 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9818 …__IO uint32_t GPIO_017_PIN_CONTROL; /*!< (@ 0x4008103C) GPIO 017 Pin Control …
9821 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9825 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9829 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9837 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9840 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9849 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9856 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9864 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9874 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9879 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9899 …__IO uint32_t GPIO_020_PIN_CONTROL; /*!< (@ 0x40081040) GPIO 020 Pin Control …
9902 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9906 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9910 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9918 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
9921 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
9930 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
9937 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
9945 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
9955 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
9960 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
9980 …__IO uint32_t GPIO_021_PIN_CONTROL; /*!< (@ 0x40081044) GPIO 021 Pin Control …
9983 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
9987 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
9991 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
9999 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10002 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10011 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10018 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10026 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10036 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10041 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10061 …__IO uint32_t GPIO_022_PIN_CONTROL; /*!< (@ 0x40081048) GPIO 022 Pin Control …
10064 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10068 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10072 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10080 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10083 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10092 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10099 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10107 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10117 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10122 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10142 …__IO uint32_t GPIO_023_PIN_CONTROL; /*!< (@ 0x4008104C) GPIO 023 Pin Control …
10145 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10149 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10153 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10161 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10164 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10173 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10180 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10188 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10198 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10203 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10223 …__IO uint32_t GPIO_024_PIN_CONTROL; /*!< (@ 0x40081050) GPIO 024 Pin Control …
10226 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10230 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10234 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10242 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10245 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10254 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10261 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10269 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10279 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10284 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10304 …__IO uint32_t GPIO_025_PIN_CONTROL; /*!< (@ 0x40081054) GPIO 025 Pin Control …
10307 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10311 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10315 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10323 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10326 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10335 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10342 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10350 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10360 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10365 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10385 …__IO uint32_t GPIO_026_PIN_CONTROL; /*!< (@ 0x40081058) GPIO 026 Pin Control …
10388 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10392 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10396 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10404 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10407 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10416 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10423 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10431 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10441 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10446 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10466 …__IO uint32_t GPIO_027_PIN_CONTROL; /*!< (@ 0x4008105C) GPIO 027 Pin Control …
10469 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10473 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10477 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10485 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10488 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10497 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10504 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10512 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10522 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10527 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10547 …__IO uint32_t GPIO_030_PIN_CONTROL; /*!< (@ 0x40081060) GPIO 030 Pin Control …
10550 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10554 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10558 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10566 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10569 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10578 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10585 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10593 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10603 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10608 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10628 …__IO uint32_t GPIO_031_PIN_CONTROL; /*!< (@ 0x40081064) GPIO 031 Pin Control …
10631 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10635 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10639 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10647 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10650 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10659 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10666 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10674 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10684 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10689 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10709 …__IO uint32_t GPIO_032_PIN_CONTROL; /*!< (@ 0x40081068) GPIO 032 Pin Control …
10712 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10716 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10720 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10728 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10731 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10740 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10747 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10755 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10765 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10770 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10790 …__IO uint32_t GPIO_033_PIN_CONTROL; /*!< (@ 0x4008106C) GPIO 033 Pin Control …
10793 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10797 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10801 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10809 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10812 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10821 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10828 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10836 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10846 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10851 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10871 …__IO uint32_t GPIO_034_PIN_CONTROL; /*!< (@ 0x40081070) GPIO 034 Pin Control …
10874 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10878 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10882 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10890 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10893 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10902 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10909 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10917 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
10927 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
10932 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
10952 …__IO uint32_t GPIO_035_PIN_CONTROL; /*!< (@ 0x40081074) GPIO 035 Pin Control …
10955 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
10959 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
10963 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
10971 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
10974 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
10983 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
10990 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
10998 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11008 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11013 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11033 …__IO uint32_t GPIO_036_PIN_CONTROL; /*!< (@ 0x40081078) GPIO 036 Pin Control …
11036 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11040 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11044 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11052 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11055 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11064 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11071 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11079 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11089 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11094 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11127 …__IO uint32_t GPIO_040_PIN_CONTROL; /*!< (@ 0x40081080) GPIO040 Pin Control …
11130 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11134 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11143 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11151 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11154 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11163 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11170 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11178 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11188 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11193 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11213 …__IO uint32_t GPIO_041_PIN_CONTROL; /*!< (@ 0x40081084) GPIO 041 Pin Control …
11216 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11220 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11229 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11237 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11240 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11249 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11256 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11264 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11274 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11279 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11299 …__IO uint32_t GPIO_042_PIN_CONTROL; /*!< (@ 0x40081088) GPIO 042 Pin Control …
11302 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11306 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11315 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11323 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11326 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11335 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11342 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11350 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11360 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11365 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11385 …__IO uint32_t GPIO_043_PIN_CONTROL; /*!< (@ 0x4008108C) GPIO 043 Pin Control …
11388 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11392 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11401 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11409 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11412 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11421 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11428 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11436 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11446 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11451 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11471 …__IO uint32_t GPIO_044_PIN_CONTROL; /*!< (@ 0x40081090) GPIO 044 Pin Control …
11474 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11478 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11487 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11495 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11498 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11507 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11514 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11522 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11532 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11537 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11557 …__IO uint32_t GPIO_045_PIN_CONTROL; /*!< (@ 0x40081094) GPIO 045 Pin Control …
11560 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11564 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11573 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11581 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11584 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11593 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11600 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11608 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11618 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11623 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11643 …__IO uint32_t GPIO_046_PIN_CONTROL; /*!< (@ 0x40081098) GPIO 046 Pin Control …
11646 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11650 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11659 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11667 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11670 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11679 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11686 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11694 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11704 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11709 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11729 …__IO uint32_t GPIO_047_PIN_CONTROL; /*!< (@ 0x4008109C) GPIO 047 Pin Control …
11732 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11736 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11745 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11753 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11756 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11765 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11772 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11780 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11790 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11795 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11815 …__IO uint32_t GPIO_050_PIN_CONTROL; /*!< (@ 0x400810A0) GPIO 050 Pin Control …
11818 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11822 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11831 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11839 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11842 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11851 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11858 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11866 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11876 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11881 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11901 …__IO uint32_t GPIO_051_PIN_CONTROL; /*!< (@ 0x400810A4) GPIO 051 Pin Control …
11904 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11908 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
11917 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
11925 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
11928 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
11937 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
11944 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
11952 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
11962 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
11967 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
11987 …__IO uint32_t GPIO_052_PIN_CONTROL; /*!< (@ 0x400810A8) GPIO 052 Pin Control …
11990 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
11994 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12003 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12011 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12014 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12023 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12030 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12038 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12048 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12053 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12073 …__IO uint32_t GPIO_053_PIN_CONTROL; /*!< (@ 0x400810AC) GPIO 053 Pin Control …
12076 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12080 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12089 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12097 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12100 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12109 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12116 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12124 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12134 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12139 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12159 …__IO uint32_t GPIO_054_PIN_CONTROL; /*!< (@ 0x400810B0) GPIO 054 Pin Control …
12162 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12166 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12175 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12183 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12186 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12195 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12202 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12210 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12220 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12225 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12245 …__IO uint32_t GPIO_055_PIN_CONTROL; /*!< (@ 0x400810B4) GPIO 055 Pin Control …
12248 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12252 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12261 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12269 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12272 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12281 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12288 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12296 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12306 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12311 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12331 …__IO uint32_t GPIO_056_PIN_CONTROL; /*!< (@ 0x400810B8) GPIO 056 Pin Control …
12334 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12338 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12347 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12355 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12358 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12367 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12374 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12382 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12392 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12397 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12417 …__IO uint32_t GPIO_057_PIN_CONTROL; /*!< (@ 0x400810BC) GPIO 057 Pin Control …
12420 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12424 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12433 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12441 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12444 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12453 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12460 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12468 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12478 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12483 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12503 …__IO uint32_t GPIO_060_PIN_CONTROL; /*!< (@ 0x400810C0) GPIO 060 Pin Control …
12506 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12510 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12519 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12527 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12530 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12539 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12546 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12554 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12564 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12569 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12589 …__IO uint32_t GPIO_061_PIN_CONTROL; /*!< (@ 0x400810C4) GPIO 061 Pin Control …
12592 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12596 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12605 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12613 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12616 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12625 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12632 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12640 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12650 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12655 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12675 …__IO uint32_t GPIO_062_PIN_CONTROL; /*!< (@ 0x400810C8) GPIO 062 Pin Control …
12678 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12682 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12691 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12699 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12702 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12711 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12718 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12726 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12736 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12741 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12761 …__IO uint32_t GPIO_063_PIN_CONTROL; /*!< (@ 0x400810CC) GPIO 063 Pin Control …
12764 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12768 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12777 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12785 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12788 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12797 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12804 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12812 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12822 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12827 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12847 …__IO uint32_t GPIO_064_PIN_CONTROL; /*!< (@ 0x400810D0) GPIO 064 Pin Control …
12850 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12854 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12863 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12871 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12874 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12883 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12890 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12898 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12908 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12913 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
12933 …__IO uint32_t GPIO_065_PIN_CONTROL; /*!< (@ 0x400810D4) GPIO 065 Pin Control …
12936 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
12940 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
12949 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
12957 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
12960 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
12969 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
12976 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
12984 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
12994 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
12999 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13019 …__IO uint32_t GPIO_066_PIN_CONTROL; /*!< (@ 0x400810D8) GPIO 066 Pin Control …
13022 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13026 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13035 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13043 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13046 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13055 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13062 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13070 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13080 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13085 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13105 …__IO uint32_t GPIO_067_PIN_CONTROL; /*!< (@ 0x400810DC) GPIO 067 Pin Control …
13108 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13112 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13121 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13129 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13132 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13141 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13148 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13156 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13166 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13171 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13191 …__IO uint32_t GPIO_070_PIN_CONTROL; /*!< (@ 0x400810E0) GPIO 070 Pin Control …
13194 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13198 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13207 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13215 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13218 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13227 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13234 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13242 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13252 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13257 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13277 …__IO uint32_t GPIO_071_PIN_CONTROL; /*!< (@ 0x400810E4) GPIO 071 Pin Control …
13280 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13284 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13293 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13301 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13304 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13313 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13320 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13328 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13338 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13343 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13363 …__IO uint32_t GPIO_072_PIN_CONTROL; /*!< (@ 0x400810E8) GPIO 072 Pin Control …
13366 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13370 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13379 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13387 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13390 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13399 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13406 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13414 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13424 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13429 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13449 …__IO uint32_t GPIO_073_PIN_CONTROL; /*!< (@ 0x400810EC) GPIO 073 Pin Control …
13452 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13456 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13465 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13473 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13476 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13485 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13492 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13500 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13510 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13515 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13535 …__IO uint32_t GPIO_074_PIN_CONTROL; /*!< (@ 0x400810F0) GPIO 074 Pin Control …
13538 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13542 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13551 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13559 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13562 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13571 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13578 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13586 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13596 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13601 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13621 …__IO uint32_t GPIO_075_PIN_CONTROL; /*!< (@ 0x400810F4) GPIO 075 Pin Control …
13624 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13628 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13637 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13645 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13648 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13657 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13664 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13672 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13682 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13687 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13707 …__IO uint32_t GPIO_076_PIN_CONTROL; /*!< (@ 0x400810F8) GPIO 076 Pin Control …
13710 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13714 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13723 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13731 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13734 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13743 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13750 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13758 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13768 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13773 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13806 …__IO uint32_t GPIO_100_PIN_CONTROL; /*!< (@ 0x40081100) GPIO100 Pin Control …
13809 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13813 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13824 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13832 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13835 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13844 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13851 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13859 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13869 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13874 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13894 …__IO uint32_t GPIO_101_PIN_CONTROL; /*!< (@ 0x40081104) GPIO 101 Pin Control …
13897 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13901 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
13912 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
13920 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
13923 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
13932 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
13939 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
13947 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
13957 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
13962 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
13982 …__IO uint32_t GPIO_102_PIN_CONTROL; /*!< (@ 0x40081108) GPIO 102 Pin Control …
13985 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
13989 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14000 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14008 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14011 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14020 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14027 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14035 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14045 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14050 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14070 …__IO uint32_t GPIO_103_PIN_CONTROL; /*!< (@ 0x4008110C) GPIO 103 Pin Control …
14073 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14077 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14088 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14096 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14099 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14108 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14115 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14123 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14133 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14138 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14158 …__IO uint32_t GPIO_104_PIN_CONTROL; /*!< (@ 0x40081110) GPIO 104 Pin Control …
14161 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14165 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14176 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14184 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14187 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14196 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14203 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14211 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14221 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14226 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14246 …__IO uint32_t GPIO_105_PIN_CONTROL; /*!< (@ 0x40081114) GPIO 105 Pin Control …
14249 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14253 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14264 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14272 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14275 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14284 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14291 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14299 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14309 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14314 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14334 …__IO uint32_t GPIO_106_PIN_CONTROL; /*!< (@ 0x40081118) GPIO 106 Pin Control …
14337 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14341 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14352 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14360 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14363 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14372 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14379 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14387 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14397 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14402 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14422 …__IO uint32_t GPIO_107_PIN_CONTROL; /*!< (@ 0x4008111C) GPIO 107 Pin Control …
14425 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14429 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14440 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14448 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14451 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14460 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14467 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14475 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14485 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14490 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14510 …__IO uint32_t GPIO_110_PIN_CONTROL; /*!< (@ 0x40081120) GPIO 110 Pin Control …
14513 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14517 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14528 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14536 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14539 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14548 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14555 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14563 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14573 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14578 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14598 …__IO uint32_t GPIO_111_PIN_CONTROL; /*!< (@ 0x40081124) GPIO 111 Pin Control …
14601 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14605 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14616 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14624 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14627 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14636 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14643 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14651 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14661 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14666 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14686 …__IO uint32_t GPIO_112_PIN_CONTROL; /*!< (@ 0x40081128) GPIO 112 Pin Control …
14689 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14693 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14704 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14712 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14715 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14724 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14731 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14739 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14749 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14754 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14774 …__IO uint32_t GPIO_113_PIN_CONTROL; /*!< (@ 0x4008112C) GPIO 113 Pin Control …
14777 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14781 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14792 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14800 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14803 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14812 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14819 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14827 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14837 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14842 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14862 …__IO uint32_t GPIO_114_PIN_CONTROL; /*!< (@ 0x40081130) GPIO 114 Pin Control …
14865 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14869 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14880 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14888 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14891 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14900 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14907 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
14915 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
14925 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
14930 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
14950 …__IO uint32_t GPIO_115_PIN_CONTROL; /*!< (@ 0x40081134) GPIO 115 Pin Control …
14953 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
14957 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
14968 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
14976 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
14979 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
14988 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
14995 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15003 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15013 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15018 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15038 …__IO uint32_t GPIO_116_PIN_CONTROL; /*!< (@ 0x40081138) GPIO 116 Pin Control …
15041 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15045 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15056 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15064 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15067 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15076 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15083 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15091 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15101 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15106 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15126 …__IO uint32_t GPIO_117_PIN_CONTROL; /*!< (@ 0x4008113C) GPIO 117 Pin Control …
15129 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15133 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15144 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15152 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15155 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15164 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15171 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15179 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15189 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15194 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15214 …__IO uint32_t GPIO_120_PIN_CONTROL; /*!< (@ 0x40081140) GPIO 120 Pin Control …
15217 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15221 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15232 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15240 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15243 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15252 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15259 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15267 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15277 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15282 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15302 …__IO uint32_t GPIO_121_PIN_CONTROL; /*!< (@ 0x40081144) GPIO 121 Pin Control …
15305 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15309 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15320 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15328 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15331 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15340 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15347 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15355 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15365 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15370 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15390 …__IO uint32_t GPIO_122_PIN_CONTROL; /*!< (@ 0x40081148) GPIO 122 Pin Control …
15393 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15397 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15408 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15416 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15419 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15428 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15435 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15443 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15453 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15458 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15478 …__IO uint32_t GPIO_123_PIN_CONTROL; /*!< (@ 0x4008114C) GPIO 123 Pin Control …
15481 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15485 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15496 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15504 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15507 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15516 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15523 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15531 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15541 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15546 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15566 …__IO uint32_t GPIO_124_PIN_CONTROL; /*!< (@ 0x40081150) GPIO 124 Pin Control …
15569 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15573 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15584 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15592 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15595 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15604 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15611 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15619 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15629 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15634 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15654 …__IO uint32_t GPIO_125_PIN_CONTROL; /*!< (@ 0x40081154) GPIO 125 Pin Control …
15657 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15661 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15672 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15680 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15683 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15692 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15699 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15707 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15717 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15722 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15742 …__IO uint32_t GPIO_126_PIN_CONTROL; /*!< (@ 0x40081158) GPIO 126 Pin Control …
15745 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15749 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15760 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15768 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15771 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15780 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15787 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15795 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15805 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15810 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15830 …__IO uint32_t GPIO_127_PIN_CONTROL; /*!< (@ 0x4008115C) GPIO 127 Pin Control …
15833 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15837 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15848 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15856 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15859 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15868 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15875 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15883 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15893 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15898 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
15918 …__IO uint32_t GPIO_130_PIN_CONTROL; /*!< (@ 0x40081160) GPIO 130 Pin Control …
15921 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
15925 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
15936 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
15944 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
15947 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
15956 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
15963 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
15971 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
15981 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
15986 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16006 …__IO uint32_t GPIO_131_PIN_CONTROL; /*!< (@ 0x40081164) GPIO 131 Pin Control …
16009 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16013 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16024 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16032 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16035 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16044 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16051 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16059 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16069 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16074 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16094 …__IO uint32_t GPIO_132_PIN_CONTROL; /*!< (@ 0x40081168) GPIO 132 Pin Control …
16097 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16101 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16112 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16120 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16123 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16132 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16139 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16147 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16157 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16162 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16182 …__IO uint32_t GPIO_133_PIN_CONTROL; /*!< (@ 0x4008116C) GPIO 133 Pin Control …
16185 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16189 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16200 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16208 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16211 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16220 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16227 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16235 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16245 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16250 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16270 …__IO uint32_t GPIO_134_PIN_CONTROL; /*!< (@ 0x40081170) GPIO 134 Pin Control …
16273 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16277 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16288 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16296 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16299 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16308 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16315 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16323 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16333 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16338 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16358 …__IO uint32_t GPIO_135_PIN_CONTROL; /*!< (@ 0x40081174) GPIO 135 Pin Control …
16361 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16365 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16376 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16384 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16387 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16396 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16403 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16411 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16421 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16426 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16459 …__IO uint32_t GPIO_140_PIN_CONTROL; /*!< (@ 0x40081180) GPIO140 Pin Control …
16462 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16466 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16470 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16478 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16481 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16490 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16497 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16505 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16515 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16520 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16540 …__IO uint32_t GPIO_141_PIN_CONTROL; /*!< (@ 0x40081184) GPIO 141 Pin Control …
16543 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16547 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16551 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16559 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16562 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16571 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16578 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16586 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16596 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16601 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16621 …__IO uint32_t GPIO_142_PIN_CONTROL; /*!< (@ 0x40081188) GPIO 142 Pin Control …
16624 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16628 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16632 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16640 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16643 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16652 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16659 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16667 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16677 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16682 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16702 …__IO uint32_t GPIO_143_PIN_CONTROL; /*!< (@ 0x4008118C) GPIO 143 Pin Control …
16705 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16709 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16713 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16721 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16724 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16733 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16740 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16748 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16758 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16763 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16783 …__IO uint32_t GPIO_144_PIN_CONTROL; /*!< (@ 0x40081190) GPIO 144 Pin Control …
16786 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16790 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16794 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16802 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16805 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16814 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16821 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16829 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16839 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16844 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16864 …__IO uint32_t GPIO_145_PIN_CONTROL; /*!< (@ 0x40081194) GPIO 145 Pin Control …
16867 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16871 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16875 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16883 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16886 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16895 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16902 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16910 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
16920 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
16925 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
16945 …__IO uint32_t GPIO_146_PIN_CONTROL; /*!< (@ 0x40081198) GPIO 146 Pin Control …
16948 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
16952 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
16956 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
16964 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
16967 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
16976 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
16983 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
16991 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17001 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17006 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17026 …__IO uint32_t GPIO_147_PIN_CONTROL; /*!< (@ 0x4008119C) GPIO 147 Pin Control …
17029 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17033 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17037 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17045 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17048 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17057 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17064 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17072 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17082 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17087 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17107 …__IO uint32_t GPIO_150_PIN_CONTROL; /*!< (@ 0x400811A0) GPIO 150 Pin Control …
17110 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17114 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17118 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17126 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17129 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17138 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17145 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17153 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17163 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17168 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17188 …__IO uint32_t GPIO_151_PIN_CONTROL; /*!< (@ 0x400811A4) GPIO 151 Pin Control …
17191 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17195 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17199 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17207 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17210 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17219 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17226 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17234 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17244 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17249 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17269 …__IO uint32_t GPIO_152_PIN_CONTROL; /*!< (@ 0x400811A8) GPIO 152 Pin Control …
17272 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17276 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17280 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17288 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17291 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17300 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17307 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17315 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17325 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17330 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17350 …__IO uint32_t GPIO_153_PIN_CONTROL; /*!< (@ 0x400811AC) GPIO 153 Pin Control …
17353 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17357 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17361 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17369 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17372 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17381 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17388 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17396 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17406 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17411 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17431 …__IO uint32_t GPIO_154_PIN_CONTROL; /*!< (@ 0x400811B0) GPIO 154 Pin Control …
17434 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17438 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17442 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17450 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17453 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17462 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17469 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17477 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17487 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17492 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17512 …__IO uint32_t GPIO_155_PIN_CONTROL; /*!< (@ 0x400811B4) GPIO 155 Pin Control …
17515 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17519 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17523 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17531 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17534 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17543 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17550 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17558 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17568 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17573 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17593 …__IO uint32_t GPIO_156_PIN_CONTROL; /*!< (@ 0x400811B8) GPIO 156 Pin Control …
17596 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17600 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17604 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17612 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17615 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17624 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17631 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17639 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17649 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17654 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17674 …__IO uint32_t GPIO_157_PIN_CONTROL; /*!< (@ 0x400811BC) GPIO 157 Pin Control …
17677 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17681 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17685 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17693 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17696 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17705 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17712 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17720 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17730 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17735 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17755 …__IO uint32_t GPIO_160_PIN_CONTROL; /*!< (@ 0x400811C0) GPIO 160 Pin Control …
17758 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17762 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17766 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17774 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17777 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17786 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17793 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17801 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17811 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17816 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17836 …__IO uint32_t GPIO_161_PIN_CONTROL; /*!< (@ 0x400811C4) GPIO 161 Pin Control …
17839 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17843 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17847 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17855 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17858 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17867 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17874 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17882 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17892 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17897 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17917 …__IO uint32_t GPIO_162_PIN_CONTROL; /*!< (@ 0x400811C8) GPIO 162 Pin Control …
17920 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
17924 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
17928 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
17936 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
17939 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
17948 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
17955 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
17963 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
17973 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
17978 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
17998 …__IO uint32_t GPIO_163_PIN_CONTROL; /*!< (@ 0x400811CC) GPIO 163 Pin Control …
18001 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18005 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18009 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18017 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18020 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18029 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18036 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18044 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18054 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18059 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18079 …__IO uint32_t GPIO_164_PIN_CONTROL; /*!< (@ 0x400811D0) GPIO 164 Pin Control …
18082 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18086 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18090 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18098 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18101 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18110 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18117 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18125 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18135 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18140 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18160 …__IO uint32_t GPIO_165_PIN_CONTROL; /*!< (@ 0x400811D4) GPIO 165 Pin Control …
18163 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18167 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18171 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18179 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18182 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18191 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18198 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18206 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18216 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18221 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18241 …__IO uint32_t GPIO_166_PIN_CONTROL; /*!< (@ 0x400811D8) GPIO 166 Pin Control …
18244 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18248 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18252 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18260 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18263 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18272 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18279 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18287 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18297 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18302 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18322 …__IO uint32_t GPIO_167_PIN_CONTROL; /*!< (@ 0x400811DC) GPIO 167 Pin Control …
18325 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18329 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18333 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18341 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18344 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18353 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18360 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18368 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18378 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18383 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18403 …__IO uint32_t GPIO_170_PIN_CONTROL; /*!< (@ 0x400811E0) GPIO 170 Pin Control …
18406 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18410 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18414 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18422 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18425 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18434 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18441 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18449 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18459 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18464 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18484 …__IO uint32_t GPIO_171_PIN_CONTROL; /*!< (@ 0x400811E4) GPIO 171 Pin Control …
18487 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18491 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18495 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18503 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18506 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18515 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18522 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18530 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18540 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18545 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18565 …__IO uint32_t GPIO_172_PIN_CONTROL; /*!< (@ 0x400811E8) GPIO 172 Pin Control …
18568 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18572 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18576 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18584 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18587 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18596 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18603 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18611 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18621 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18626 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18646 …__IO uint32_t GPIO_173_PIN_CONTROL; /*!< (@ 0x400811EC) GPIO 173 Pin Control …
18649 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18653 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18657 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18665 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18668 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18677 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18684 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18692 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18702 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18707 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18727 …__IO uint32_t GPIO_174_PIN_CONTROL; /*!< (@ 0x400811F0) GPIO 174 Pin Control …
18730 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18734 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18738 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18746 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18749 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18758 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18765 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18773 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18783 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18788 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18808 …__IO uint32_t GPIO_175_PIN_CONTROL; /*!< (@ 0x400811F4) GPIO 175 Pin Control …
18811 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18815 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18819 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18827 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18830 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18839 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18846 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18854 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18864 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18869 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18902 …__IO uint32_t GPIO_200_PIN_CONTROL; /*!< (@ 0x40081200) GPIO200 Pin Control …
18905 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18909 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18913 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
18921 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
18924 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
18933 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
18940 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
18948 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
18958 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
18963 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
18983 …__IO uint32_t GPIO_201_PIN_CONTROL; /*!< (@ 0x40081204) GPIO 201 Pin Control …
18986 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
18990 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
18994 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19002 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19005 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19014 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19021 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19029 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19039 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19044 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19064 …__IO uint32_t GPIO_202_PIN_CONTROL; /*!< (@ 0x40081208) GPIO 202 Pin Control …
19067 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19071 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19075 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19083 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19086 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19095 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19102 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19110 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19120 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19125 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19145 …__IO uint32_t GPIO_203_PIN_CONTROL; /*!< (@ 0x4008120C) GPIO 203 Pin Control …
19148 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19152 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19156 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19164 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19167 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19176 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19183 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19191 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19201 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19206 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19226 …__IO uint32_t GPIO_204_PIN_CONTROL; /*!< (@ 0x40081210) GPIO 204 Pin Control …
19229 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19233 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19237 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19245 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19248 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19257 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19264 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19272 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19282 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19287 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19307 …__IO uint32_t GPIO_205_PIN_CONTROL; /*!< (@ 0x40081214) GPIO 205 Pin Control …
19310 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19314 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19318 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19326 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19329 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19338 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19345 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19353 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19363 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19368 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19388 …__IO uint32_t GPIO_206_PIN_CONTROL; /*!< (@ 0x40081218) GPIO 206 Pin Control …
19391 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19395 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19399 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19407 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19410 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19419 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19426 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19434 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19444 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19449 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19469 …__IO uint32_t GPIO_207_PIN_CONTROL; /*!< (@ 0x4008121C) GPIO 207 Pin Control …
19472 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19476 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19480 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19488 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19491 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19500 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19507 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19515 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19525 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19530 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19550 …__IO uint32_t GPIO_210_PIN_CONTROL; /*!< (@ 0x40081220) GPIO 210 Pin Control …
19553 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19557 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19561 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19569 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19572 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19581 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19588 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19596 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19606 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19611 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19631 …__IO uint32_t GPIO_211_PIN_CONTROL; /*!< (@ 0x40081224) GPIO 211 Pin Control …
19634 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19638 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19642 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19650 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19653 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19662 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19669 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19677 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19687 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19692 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19712 …__IO uint32_t GPIO_212_PIN_CONTROL; /*!< (@ 0x40081228) GPIO 212 Pin Control …
19715 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19719 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19723 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19731 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19734 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19743 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19750 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19758 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19768 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19773 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19793 …__IO uint32_t GPIO_213_PIN_CONTROL; /*!< (@ 0x4008122C) GPIO 213 Pin Control …
19796 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19800 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19804 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19812 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19815 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19824 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19831 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19839 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19849 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19854 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19874 …__IO uint32_t GPIO_214_PIN_CONTROL; /*!< (@ 0x40081230) GPIO 214 Pin Control …
19877 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19881 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19885 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19893 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19896 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19905 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19912 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
19920 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
19930 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
19935 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
19955 …__IO uint32_t GPIO_215_PIN_CONTROL; /*!< (@ 0x40081234) GPIO 215 Pin Control …
19958 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
19962 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
19966 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
19974 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
19977 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
19986 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
19993 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20001 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20011 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20016 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20036 …__IO uint32_t GPIO_216_PIN_CONTROL; /*!< (@ 0x40081238) GPIO 216 Pin Control …
20039 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20043 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20047 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20055 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20058 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20067 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20074 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20082 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20092 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20097 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20117 …__IO uint32_t GPIO_217_PIN_CONTROL; /*!< (@ 0x4008123C) GPIO 217 Pin Control …
20120 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20124 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20128 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20136 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20139 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20148 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20155 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20163 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20173 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20178 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20199 …__IO uint32_t GPIO_221_PIN_CONTROL; /*!< (@ 0x40081244) GPIO 221 Pin Control …
20202 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20206 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20210 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20218 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20221 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20230 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20237 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20245 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20255 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20260 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20280 …__IO uint32_t GPIO_222_PIN_CONTROL; /*!< (@ 0x40081248) GPIO 222 Pin Control …
20283 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20287 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20291 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20299 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20302 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20311 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20318 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20326 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20336 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20341 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20361 …__IO uint32_t GPIO_223_PIN_CONTROL; /*!< (@ 0x4008124C) GPIO 223 Pin Control …
20364 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20368 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20372 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20380 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20383 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20392 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20399 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20407 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20417 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20422 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20442 …__IO uint32_t GPIO_224_PIN_CONTROL; /*!< (@ 0x40081250) GPIO 224 Pin Control …
20445 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20449 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20453 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20461 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20464 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20473 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20480 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20488 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20498 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20503 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20523 …__IO uint32_t GPIO_225_PIN_CONTROL; /*!< (@ 0x40081254) GPIO 225 Pin Control …
20526 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20530 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20534 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20542 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20545 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20554 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20561 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20569 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20579 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20584 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20604 …__IO uint32_t GPIO_226_PIN_CONTROL; /*!< (@ 0x40081258) GPIO 226 Pin Control …
20607 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20611 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20615 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20623 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20626 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20635 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20642 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20650 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20660 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20665 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20685 …__IO uint32_t GPIO_227_PIN_CONTROL; /*!< (@ 0x4008125C) GPIO 227 Pin Control …
20688 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20692 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20696 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20704 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20707 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20716 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20723 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20731 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20741 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20746 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20766 …__IO uint32_t GPIO_230_PIN_CONTROL; /*!< (@ 0x40081260) GPIO 230 Pin Control …
20769 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20773 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20777 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20785 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20788 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20797 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20804 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20812 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20822 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20827 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20847 …__IO uint32_t GPIO_231_PIN_CONTROL; /*!< (@ 0x40081264) GPIO 231 Pin Control …
20850 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20854 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20858 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20866 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20869 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20878 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20885 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20893 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20903 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20908 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
20928 …__IO uint32_t GPIO_232_PIN_CONTROL; /*!< (@ 0x40081268) GPIO 232 Pin Control …
20931 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
20935 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
20939 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
20947 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
20950 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
20959 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
20966 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
20974 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
20984 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
20989 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21009 …__IO uint32_t GPIO_233_PIN_CONTROL; /*!< (@ 0x4008126C) GPIO 233 Pin Control …
21012 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21016 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21020 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21028 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21031 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21040 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21047 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21055 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21065 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21070 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21090 …__IO uint32_t GPIO_234_PIN_CONTROL; /*!< (@ 0x40081270) GPIO 234 Pin Control …
21093 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21097 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21101 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21109 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21112 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21121 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21128 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21136 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21146 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21151 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21171 …__IO uint32_t GPIO_235_PIN_CONTROL; /*!< (@ 0x40081274) GPIO 235 Pin Control …
21174 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21178 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21182 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21190 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21193 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21202 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21209 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21217 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21227 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21232 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21265 …__IO uint32_t GPIO_240_PIN_CONTROL; /*!< (@ 0x40081280) GPIO240 Pin Control …
21268 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21272 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21276 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21284 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21287 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21296 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21303 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21311 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21321 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21326 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21346 …__IO uint32_t GPIO_241_PIN_CONTROL; /*!< (@ 0x40081284) GPIO 241 Pin Control …
21349 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21353 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21357 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21365 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21368 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21377 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21384 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21392 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21402 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21407 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21427 …__IO uint32_t GPIO_242_PIN_CONTROL; /*!< (@ 0x40081288) GPIO 242 Pin Control …
21430 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21434 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21438 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21446 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21449 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21458 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21465 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21473 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21483 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21488 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21508 …__IO uint32_t GPIO_243_PIN_CONTROL; /*!< (@ 0x4008128C) GPIO 243 Pin Control …
21511 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21515 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21519 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21527 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21530 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21539 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21546 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21554 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21564 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21569 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21589 …__IO uint32_t GPIO_244_PIN_CONTROL; /*!< (@ 0x40081290) GPIO 244 Pin Control …
21592 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21596 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21600 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21608 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21611 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21620 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21627 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21635 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21645 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21650 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21670 …__IO uint32_t GPIO_245_PIN_CONTROL; /*!< (@ 0x40081294) GPIO 245 Pin Control …
21673 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21677 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21681 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21689 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21692 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21701 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21708 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21716 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21726 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21731 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21751 …__IO uint32_t GPIO_246_PIN_CONTROL; /*!< (@ 0x40081298) GPIO 246 Pin Control …
21754 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21758 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21762 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21770 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21773 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21782 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21789 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21797 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21807 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21812 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21833 …__IO uint32_t GPIO_250_PIN_CONTROL; /*!< (@ 0x400812A0) GPIO 250 Pin Control …
21836 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21840 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21844 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21852 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21855 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21864 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21871 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21879 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21889 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21894 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21915 …__IO uint32_t GPIO_253_PIN_CONTROL; /*!< (@ 0x400812AC) GPIO 253 Pin Control …
21918 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
21922 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
21926 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
21934 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
21937 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
21946 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
21953 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
21961 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
21971 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
21976 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
21996 …__IO uint32_t GPIO_254_PIN_CONTROL; /*!< (@ 0x400812B0) GPIO 254 Pin Control …
21999 …__IO uint32_t PU_PD : 2; /*!< [0..1] These bits are used to enable an interna…
22003 …__IO uint32_t POWER_GATING: 2; /*!< [2..3] The GPIO pin will be tristated when the …
22007 …__IO uint32_t INTERRUPT_DETECTION: 3; /*!< [4..6] When combined with the field INTERRUPT_D…
22015 …__IO uint32_t EDGE_ENABLE: 1; /*!< [7..7] When combined with the field INTERRUPT_D…
22018 …__IO uint32_t OUTPUT_BUFFER_TYPE: 1; /*!< [8..8] Unless explicitly stated otherwise, pins…
22027 …__IO uint32_t GPIO_DIRECTION: 1; /*!< [9..9] This bit controls the buffer direction o…
22034 …__IO uint32_t GPIO_OUTPUT_SELECT: 1; /*!< [10..10] This control bit determines which regi…
22042 …__IO uint32_t POLARITY : 1; /*!< [11..11] When the Polarity bit is set to '1' an…
22052 …__IO uint32_t MUX_CONTROL: 2; /*!< [12..13] This field determines the active signa…
22057 …__IO uint32_t ALTERNATE_GPIO_DATA: 1; /*!< [16..16] Reads of this bit always return the la…
22088 …__IO uint32_t INPUT_GPIO_000_036; /*!< (@ 0x40081300) The GPIO Input Registers can…
22093 …__IO uint32_t INPUT_GPIO_040_076; /*!< (@ 0x40081304) Input GPIO[040:076] …
22094 …__IO uint32_t INPUT_GPIO_100_136; /*!< (@ 0x40081308) Input GPIO[100:136] …
22095 …__IO uint32_t INPUT_GPIO_140_176; /*!< (@ 0x4008130C) Input GPIO[140:176] …
22096 …__IO uint32_t INPUT_GPIO_200_236; /*!< (@ 0x40081310) Input GPIO[200:236] …
22097 …__IO uint32_t INPUT_GPIO_240_276; /*!< (@ 0x40081314) Input GPIO[240:276] …
22099 …__IO uint32_t OUTPUT_GPIO_000_036; /*!< (@ 0x40081380) If enabled by the Output GPI…
22105 …__IO uint32_t OUPUT_GPIO_040_076; /*!< (@ 0x40081384) Output GPIO[040:076] …
22106 …__IO uint32_t OUTPUT_GPIO_100_136; /*!< (@ 0x40081388) Output GPIO[100:136] …
22107 …__IO uint32_t OUTPUT_GPIO_140_176; /*!< (@ 0x4008138C) Output GPIO[140:176] …
22108 …__IO uint32_t OUTPUT_GPIO_200_236; /*!< (@ 0x40081390) Output GPIO[200:236] …
22109 …__IO uint32_t OUTPUT_GPIO_240_276; /*!< (@ 0x40081394) Output GPIO[240:276] …
22125 …__IO uint32_t GPIO_000_PIN_CONTROL_2; /*!< (@ 0x40081500) GPIO 000 PIN CONTROL REGISTER …
22128 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22131 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22139 …__IO uint32_t GPIO_001_PIN_CONTROL_2; /*!< (@ 0x40081504) GPIO 001 Pin Control 2 …
22142 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22145 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22153 …__IO uint32_t GPIO_002_PIN_CONTROL_2; /*!< (@ 0x40081508) GPIO 002 Pin Control 2 …
22156 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22159 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22167 …__IO uint32_t GPIO_003_PIN_CONTROL_2; /*!< (@ 0x4008150C) GPIO 003 Pin Control 2 …
22170 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22173 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22181 …__IO uint32_t GPIO_004_PIN_CONTROL_2; /*!< (@ 0x40081510) GPIO 004 Pin Control 2 …
22184 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22187 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22195 …__IO uint32_t GPIO_005_PIN_CONTROL_2; /*!< (@ 0x40081514) GPIO 005 Pin Control 2 …
22198 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22201 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22209 …__IO uint32_t GPIO_006_PIN_CONTROL_2; /*!< (@ 0x40081518) GPIO 006 Pin Control 2 …
22212 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22215 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22223 …__IO uint32_t GPIO_007_PIN_CONTROL_2; /*!< (@ 0x4008151C) GPIO 007 Pin Control 2 …
22226 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22229 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22237 …__IO uint32_t GPIO_010_PIN_CONTROL_2; /*!< (@ 0x40081520) GPIO 010 Pin Control 2 …
22240 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22243 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22251 …__IO uint32_t GPIO_011_PIN_CONTROL_2; /*!< (@ 0x40081524) GPIO 011 Pin Control 2 …
22254 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22257 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22265 …__IO uint32_t GPIO_012_PIN_CONTROL_2; /*!< (@ 0x40081528) GPIO 012 Pin Control 2 …
22268 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22271 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22279 …__IO uint32_t GPIO_013_PIN_CONTROL_2; /*!< (@ 0x4008152C) GPIO 013 Pin Control 2 …
22282 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22285 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22293 …__IO uint32_t GPIO_014_PIN_CONTROL_2; /*!< (@ 0x40081530) GPIO 014 Pin Control 2 …
22296 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22299 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22307 …__IO uint32_t GPIO_015_PIN_CONTROL_2; /*!< (@ 0x40081534) GPIO 015 Pin Control 2 …
22310 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22313 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22321 …__IO uint32_t GPIO_016_PIN_CONTROL_2; /*!< (@ 0x40081538) GPIO 016 Pin Control 2 …
22324 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22327 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22335 …__IO uint32_t GPIO_017_PIN_CONTROL_2; /*!< (@ 0x4008153C) GPIO 017 Pin Control 2 …
22338 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22341 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22349 …__IO uint32_t GPIO_020_PIN_CONTROL_2; /*!< (@ 0x40081540) GPIO 020 Pin Control 2 …
22352 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22355 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22363 …__IO uint32_t GPIO_021_PIN_CONTROL_2; /*!< (@ 0x40081544) GPIO 021 Pin Control 2 …
22366 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22369 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22377 …__IO uint32_t GPIO_022_PIN_CONTROL_2; /*!< (@ 0x40081548) GPIO 022 Pin Control 2 …
22380 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22383 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22391 …__IO uint32_t GPIO_023_PIN_CONTROL_2; /*!< (@ 0x4008154C) GPIO 023 Pin Control 2 …
22394 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22397 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22405 …__IO uint32_t GPIO_024_PIN_CONTROL_2; /*!< (@ 0x40081550) GPIO 024 Pin Control 2 …
22408 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22411 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22419 …__IO uint32_t GPIO_025_PIN_CONTROL_2; /*!< (@ 0x40081554) GPIO 025 Pin Control 2 …
22422 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22425 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22433 …__IO uint32_t GPIO_026_PIN_CONTROL_2; /*!< (@ 0x40081558) GPIO 026 Pin Control 2 …
22436 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22439 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22447 …__IO uint32_t GPIO_027_PIN_CONTROL_2; /*!< (@ 0x4008155C) GPIO 027 Pin Control 2 …
22450 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22453 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22461 …__IO uint32_t GPIO_030_PIN_CONTROL_2; /*!< (@ 0x40081560) GPIO 030 Pin Control 2 …
22464 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22467 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22475 …__IO uint32_t GPIO_031_PIN_CONTROL_2; /*!< (@ 0x40081564) GPIO 031 Pin Control 2 …
22478 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22481 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22489 …__IO uint32_t GPIO_032_PIN_CONTROL_2; /*!< (@ 0x40081568) GPIO 032 Pin Control 2 …
22492 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22495 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22503 …__IO uint32_t GPIO_033_PIN_CONTROL_2; /*!< (@ 0x4008156C) GPIO 033 Pin Control 2 …
22506 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22509 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22517 …__IO uint32_t GPIO_034_PIN_CONTROL_2; /*!< (@ 0x40081570) GPIO 034 Pin Control 2 …
22520 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22523 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22531 …__IO uint32_t GPIO_035_PIN_CONTROL_2; /*!< (@ 0x40081574) GPIO 035 Pin Control 2 …
22534 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22537 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22545 …__IO uint32_t GPIO_036_PIN_CONTROL_2; /*!< (@ 0x40081578) GPIO 036 Pin Control 2 …
22548 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22551 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22560 …__IO uint32_t GPIO_040_PIN_CONTROL_2; /*!< (@ 0x40081580) GPIO 040 Pin Control 2 …
22563 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22566 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22574 …__IO uint32_t GPIO_041_PIN_CONTROL_2; /*!< (@ 0x40081584) GPIO 041 Pin Control 2 …
22577 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22580 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22588 …__IO uint32_t GPIO_042_PIN_CONTROL_2; /*!< (@ 0x40081588) GPIO 042 Pin Control 2 …
22591 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22594 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22602 …__IO uint32_t GPIO_043_PIN_CONTROL_2; /*!< (@ 0x4008158C) GPIO 043 Pin Control 2 …
22605 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22608 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22616 …__IO uint32_t GPIO_044_PIN_CONTROL_2; /*!< (@ 0x40081590) GPIO 044 Pin Control 2 …
22619 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22622 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22630 …__IO uint32_t GPIO_045_PIN_CONTROL_2; /*!< (@ 0x40081594) GPIO 045 Pin Control 2 …
22633 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22636 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22644 …__IO uint32_t GPIO_046_PIN_CONTROL_2; /*!< (@ 0x40081598) GPIO 046 Pin Control 2 …
22647 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22650 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22658 …__IO uint32_t GPIO_047_PIN_CONTROL_2; /*!< (@ 0x4008159C) GPIO 047 Pin Control 2 …
22661 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22664 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22672 …__IO uint32_t GPIO_050_PIN_CONTROL_2; /*!< (@ 0x400815A0) GPIO 050 Pin Control 2 …
22675 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22678 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22686 …__IO uint32_t GPIO_051_PIN_CONTROL_2; /*!< (@ 0x400815A4) GPIO 051 Pin Control 2 …
22689 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22692 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22700 …__IO uint32_t GPIO_052_PIN_CONTROL_2; /*!< (@ 0x400815A8) GPIO 052 Pin Control 2 …
22703 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22706 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22714 …__IO uint32_t GPIO_053_PIN_CONTROL_2; /*!< (@ 0x400815AC) GPIO 053 Pin Control 2 …
22717 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22720 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22728 …__IO uint32_t GPIO_054_PIN_CONTROL_2; /*!< (@ 0x400815B0) GPIO 054 Pin Control 2 …
22731 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22734 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22742 …__IO uint32_t GPIO_055_PIN_CONTROL_2; /*!< (@ 0x400815B4) GPIO 055 Pin Control 2 …
22745 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22748 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22756 …__IO uint32_t GPIO_056_PIN_CONTROL_2; /*!< (@ 0x400815B8) GPIO 056 Pin Control 2 …
22759 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22762 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22770 …__IO uint32_t GPIO_057_PIN_CONTROL_2; /*!< (@ 0x400815BC) GPIO 057 Pin Control 2 …
22773 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22776 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22784 …__IO uint32_t GPIO_060_PIN_CONTROL_2; /*!< (@ 0x400815C0) GPIO 060 Pin Control 2 …
22787 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22790 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22798 …__IO uint32_t GPIO_061_PIN_CONTROL_2; /*!< (@ 0x400815C4) GPIO 061 Pin Control 2 …
22801 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22804 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22812 …__IO uint32_t GPIO_062_PIN_CONTROL_2; /*!< (@ 0x400815C8) GPIO 062 Pin Control 2 …
22815 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22818 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22826 …__IO uint32_t GPIO_063_PIN_CONTROL_2; /*!< (@ 0x400815CC) GPIO 063 Pin Control 2 …
22829 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22832 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22840 …__IO uint32_t GPIO_064_PIN_CONTROL_2; /*!< (@ 0x400815D0) GPIO 064 Pin Control 2 …
22843 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22846 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22854 …__IO uint32_t GPIO_065_PIN_CONTROL_2; /*!< (@ 0x400815D4) GPIO 065 Pin Control 2 …
22857 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22860 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22868 …__IO uint32_t GPIO_066_PIN_CONTROL_2; /*!< (@ 0x400815D8) GPIO 066 Pin Control 2 …
22871 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22874 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22882 …__IO uint32_t GPIO_067_PIN_CONTROL_2; /*!< (@ 0x400815DC) GPIO 067 Pin Control 2 …
22885 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22888 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22896 …__IO uint32_t GPIO_070_PIN_CONTROL_2; /*!< (@ 0x400815E0) GPIO 070 Pin Control 2 …
22899 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22902 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22910 …__IO uint32_t GPIO_071_PIN_CONTROL_2; /*!< (@ 0x400815E4) GPIO 071 Pin Control 2 …
22913 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22916 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22924 …__IO uint32_t GPIO_072_PIN_CONTROL_2; /*!< (@ 0x400815E8) GPIO 072 Pin Control 2 …
22927 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22930 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22938 …__IO uint32_t GPIO_073_PIN_CONTROL_2; /*!< (@ 0x400815EC) GPIO 073 Pin Control 2 …
22941 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22944 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22952 …__IO uint32_t GPIO_074_PIN_CONTROL_2; /*!< (@ 0x400815F0) GPIO 074 Pin Control 2 …
22955 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22958 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22966 …__IO uint32_t GPIO_075_PIN_CONTROL_2; /*!< (@ 0x400815F4) GPIO 075 Pin Control 2 …
22969 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22972 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22980 …__IO uint32_t GPIO_076_PIN_CONTROL_2; /*!< (@ 0x400815F8) GPIO 076 Pin Control 2 …
22983 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
22986 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
22995 …__IO uint32_t GPIO_100_PIN_CONTROL_2; /*!< (@ 0x40081600) GPIO 100 Pin Control 2 …
22998 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23001 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23009 …__IO uint32_t GPIO_101_PIN_CONTROL_2; /*!< (@ 0x40081604) GPIO 101 Pin Control 2 …
23012 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23015 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23023 …__IO uint32_t GPIO_102_PIN_CONTROL_2; /*!< (@ 0x40081608) GPIO 102 Pin Control 2 …
23026 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23029 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23037 …__IO uint32_t GPIO_103_PIN_CONTROL_2; /*!< (@ 0x4008160C) GPIO 103 Pin Control 2 …
23040 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23043 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23051 …__IO uint32_t GPIO_104_PIN_CONTROL_2; /*!< (@ 0x40081610) GPIO 104 Pin Control 2 …
23054 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23057 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23065 …__IO uint32_t GPIO_105_PIN_CONTROL_2; /*!< (@ 0x40081614) GPIO 105 Pin Control 2 …
23068 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23071 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23079 …__IO uint32_t GPIO_106_PIN_CONTROL_2; /*!< (@ 0x40081618) GPIO 106 Pin Control 2 …
23082 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23085 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23093 …__IO uint32_t GPIO_107_PIN_CONTROL_2; /*!< (@ 0x4008161C) GPIO 107 Pin Control 2 …
23096 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23099 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23107 …__IO uint32_t GPIO_110_PIN_CONTROL_2; /*!< (@ 0x40081620) GPIO 110 Pin Control 2 …
23110 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23113 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23121 …__IO uint32_t GPIO_111_PIN_CONTROL_2; /*!< (@ 0x40081624) GPIO 111 Pin Control 2 …
23124 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23127 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23135 …__IO uint32_t GPIO_112_PIN_CONTROL_2; /*!< (@ 0x40081628) GPIO 112 Pin Control 2 …
23138 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23141 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23149 …__IO uint32_t GPIO_113_PIN_CONTROL_2; /*!< (@ 0x4008162C) GPIO 113 Pin Control 2 …
23152 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23155 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23163 …__IO uint32_t GPIO_114_PIN_CONTROL_2; /*!< (@ 0x40081630) GPIO 114 Pin Control 2 …
23166 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23169 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23177 …__IO uint32_t GPIO_115_PIN_CONTROL_2; /*!< (@ 0x40081634) GPIO 115 Pin Control 2 …
23180 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23183 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23191 …__IO uint32_t GPIO_116_PIN_CONTROL_2; /*!< (@ 0x40081638) GPIO 116 Pin Control 2 …
23194 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23197 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23205 …__IO uint32_t GPIO_117_PIN_CONTROL_2; /*!< (@ 0x4008163C) GPIO 117 Pin Control 2 …
23208 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23211 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23219 …__IO uint32_t GPIO_120_PIN_CONTROL_2; /*!< (@ 0x40081640) GPIO 120 Pin Control 2 …
23222 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23225 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23233 …__IO uint32_t GPIO_121_PIN_CONTROL_2; /*!< (@ 0x40081644) GPIO 121 Pin Control 2 …
23236 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23239 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23247 …__IO uint32_t GPIO_122_PIN_CONTROL_2; /*!< (@ 0x40081648) GPIO 122 Pin Control 2 …
23250 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23253 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23261 …__IO uint32_t GPIO_123_PIN_CONTROL_2; /*!< (@ 0x4008164C) GPIO 123 Pin Control 2 …
23264 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23267 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23275 …__IO uint32_t GPIO_124_PIN_CONTROL_2; /*!< (@ 0x40081650) GPIO 124 Pin Control 2 …
23278 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23281 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23289 …__IO uint32_t GPIO_125_PIN_CONTROL_2; /*!< (@ 0x40081654) GPIO 125 Pin Control 2 …
23292 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23295 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23303 …__IO uint32_t GPIO_126_PIN_CONTROL_2; /*!< (@ 0x40081658) GPIO 126 Pin Control 2 …
23306 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23309 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23317 …__IO uint32_t GPIO_127_PIN_CONTROL_2; /*!< (@ 0x4008165C) GPIO 127 Pin Control 2 …
23320 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23323 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23331 …__IO uint32_t GPIO_130_PIN_CONTROL_2; /*!< (@ 0x40081660) GPIO 130 Pin Control 2 …
23334 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23337 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23345 …__IO uint32_t GPIO_131_PIN_CONTROL_2; /*!< (@ 0x40081664) GPIO 131 Pin Control 2 …
23348 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23351 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23359 …__IO uint32_t GPIO_132_PIN_CONTROL_2; /*!< (@ 0x40081668) GPIO 132 Pin Control 2 …
23362 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23365 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23373 …__IO uint32_t GPIO_133_PIN_CONTROL_2; /*!< (@ 0x4008166C) GPIO 133 Pin Control 2 …
23376 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23379 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23387 …__IO uint32_t GPIO_134_PIN_CONTROL_2; /*!< (@ 0x40081670) GPIO 134 Pin Control 2 …
23390 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23393 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23401 …__IO uint32_t GPIO_135_PIN_CONTROL_2; /*!< (@ 0x40081674) GPIO 135 Pin Control 2 …
23404 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23407 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23416 …__IO uint32_t GPIO_140_PIN_CONTROL_2; /*!< (@ 0x40081680) GPIO 140 Pin Control 2 …
23419 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23422 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23430 …__IO uint32_t GPIO_141_PIN_CONTROL_2; /*!< (@ 0x40081684) GPIO 141 Pin Control 2 …
23433 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23436 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23444 …__IO uint32_t GPIO_142_PIN_CONTROL_2; /*!< (@ 0x40081688) GPIO 142 Pin Control 2 …
23447 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23450 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23458 …__IO uint32_t GPIO_143_PIN_CONTROL_2; /*!< (@ 0x4008168C) GPIO 143 Pin Control 2 …
23461 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23464 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23472 …__IO uint32_t GPIO_144_PIN_CONTROL_2; /*!< (@ 0x40081690) GPIO 144 Pin Control 2 …
23475 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23478 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23486 …__IO uint32_t GPIO_145_PIN_CONTROL_2; /*!< (@ 0x40081694) GPIO 145 Pin Control 2 …
23489 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23492 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23500 …__IO uint32_t GPIO_146_PIN_CONTROL_2; /*!< (@ 0x40081698) GPIO 146 Pin Control 2 …
23503 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23506 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23514 …__IO uint32_t GPIO_147_PIN_CONTROL_2; /*!< (@ 0x4008169C) GPIO 147 Pin Control 2 …
23517 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23520 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23528 …__IO uint32_t GPIO_150_PIN_CONTROL_2; /*!< (@ 0x400816A0) GPIO 150 Pin Control 2 …
23531 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23534 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23542 …__IO uint32_t GPIO_151_PIN_CONTROL_2; /*!< (@ 0x400816A4) GPIO 151 Pin Control 2 …
23545 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23548 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23556 …__IO uint32_t GPIO_152_PIN_CONTROL_2; /*!< (@ 0x400816A8) GPIO 152 Pin Control 2 …
23559 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23562 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23570 …__IO uint32_t GPIO_153_PIN_CONTROL_2; /*!< (@ 0x400816AC) GPIO 153 Pin Control 2 …
23573 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23576 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23584 …__IO uint32_t GPIO_154_PIN_CONTROL_2; /*!< (@ 0x400816B0) GPIO 154 Pin Control 2 …
23587 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23590 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23598 …__IO uint32_t GPIO_155_PIN_CONTROL_2; /*!< (@ 0x400816B4) GPIO 155 Pin Control 2 …
23601 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23604 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23612 …__IO uint32_t GPIO_156_PIN_CONTROL_2; /*!< (@ 0x400816B8) GPIO 156 Pin Control 2 …
23615 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23618 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23626 …__IO uint32_t GPIO_157_PIN_CONTROL_2; /*!< (@ 0x400816BC) GPIO 157 Pin Control 2 …
23629 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23632 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23640 …__IO uint32_t GPIO_160_PIN_CONTROL_2; /*!< (@ 0x400816C0) GPIO 160 Pin Control 2 …
23643 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23646 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23654 …__IO uint32_t GPIO_161_PIN_CONTROL_2; /*!< (@ 0x400816C4) GPIO 161 Pin Control 2 …
23657 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23660 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23668 …__IO uint32_t GPIO_162_PIN_CONTROL_2; /*!< (@ 0x400816C8) GPIO 162 Pin Control 2 …
23671 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23674 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23682 …__IO uint32_t GPIO_163_PIN_CONTROL_2; /*!< (@ 0x400816CC) GPIO 163 Pin Control 2 …
23685 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23688 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23696 …__IO uint32_t GPIO_164_PIN_CONTROL_2; /*!< (@ 0x400816D0) GPIO 164 Pin Control 2 …
23699 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23702 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23710 …__IO uint32_t GPIO_165_PIN_CONTROL_2; /*!< (@ 0x400816D4) GPIO 165 Pin Control 2 …
23713 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23716 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23724 …__IO uint32_t GPIO_166_PIN_CONTROL_2; /*!< (@ 0x400816D8) GPIO 166 Pin Control 2 …
23727 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23730 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23738 …__IO uint32_t GPIO_167_PIN_CONTROL_2; /*!< (@ 0x400816DC) GPIO 167 Pin Control 2 …
23741 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23744 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23752 …__IO uint32_t GPIO_170_PIN_CONTROL_2; /*!< (@ 0x400816E0) GPIO 170 Pin Control 2 …
23755 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23758 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23766 …__IO uint32_t GPIO_171_PIN_CONTROL_2; /*!< (@ 0x400816E4) GPIO 171 Pin Control 2 …
23769 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23772 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23780 …__IO uint32_t GPIO_172_PIN_CONTROL_2; /*!< (@ 0x400816E8) GPIO 172 Pin Control 2 …
23783 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23786 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23794 …__IO uint32_t GPIO_173_PIN_CONTROL_2; /*!< (@ 0x400816EC) GPIO 173 Pin Control 2 …
23797 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23800 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23808 …__IO uint32_t GPIO_174_PIN_CONTROL_2; /*!< (@ 0x400816F0) GPIO 174 Pin Control 2 …
23811 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23814 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23822 …__IO uint32_t GPIO_175_PIN_CONTROL_2; /*!< (@ 0x400816F4) GPIO 175 Pin Control 2 …
23825 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23828 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23837 …__IO uint32_t GPIO_200_PIN_CONTROL_2; /*!< (@ 0x40081700) GPIO 200 Pin Control 2 …
23840 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23843 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23851 …__IO uint32_t GPIO_201_PIN_CONTROL_2; /*!< (@ 0x40081704) GPIO 201 Pin Control 2 …
23854 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23857 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23865 …__IO uint32_t GPIO_202_PIN_CONTROL_2; /*!< (@ 0x40081708) GPIO 202 Pin Control 2 …
23868 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23871 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23879 …__IO uint32_t GPIO_203_PIN_CONTROL_2; /*!< (@ 0x4008170C) GPIO 203 Pin Control 2 …
23882 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23885 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23893 …__IO uint32_t GPIO_204_PIN_CONTROL_2; /*!< (@ 0x40081710) GPIO 204 Pin Control 2 …
23896 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23899 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23907 …__IO uint32_t GPIO_205_PIN_CONTROL_2; /*!< (@ 0x40081714) GPIO 205 Pin Control 2 …
23910 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23913 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23921 …__IO uint32_t GPIO_206_PIN_CONTROL_2; /*!< (@ 0x40081718) GPIO 206 Pin Control 2 …
23924 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23927 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23935 …__IO uint32_t GPIO_207_PIN_CONTROL_2; /*!< (@ 0x4008171C) GPIO 207 Pin Control 2 …
23938 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23941 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23949 …__IO uint32_t GPIO_210_PIN_CONTROL_2; /*!< (@ 0x40081720) GPIO 210 Pin Control 2 …
23952 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23955 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23963 …__IO uint32_t GPIO_211_PIN_CONTROL_2; /*!< (@ 0x40081724) GPIO 211 Pin Control 2 …
23966 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23969 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23977 …__IO uint32_t GPIO_212_PIN_CONTROL_2; /*!< (@ 0x40081728) GPIO 212 Pin Control 2 …
23980 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23983 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
23991 …__IO uint32_t GPIO_213_PIN_CONTROL_2; /*!< (@ 0x4008172C) GPIO 213 Pin Control 2 …
23994 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
23997 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24005 …__IO uint32_t GPIO_214_PIN_CONTROL_2; /*!< (@ 0x40081730) GPIO 214 Pin Control 2 …
24008 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24011 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24019 …__IO uint32_t GPIO_215_PIN_CONTROL_2; /*!< (@ 0x40081734) GPIO 215 Pin Control 2 …
24022 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24025 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24033 …__IO uint32_t GPIO_216_PIN_CONTROL_2; /*!< (@ 0x40081738) GPIO 216 Pin Control 2 …
24036 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24039 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24047 …__IO uint32_t GPIO_217_PIN_CONTROL_2; /*!< (@ 0x4008173C) GPIO 217 Pin Control 2 …
24050 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24053 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24062 …__IO uint32_t GPIO_221_PIN_CONTROL_2; /*!< (@ 0x40081744) GPIO 221 Pin Control 2 …
24065 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24068 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24076 …__IO uint32_t GPIO_222_PIN_CONTROL_2; /*!< (@ 0x40081748) GPIO 222 Pin Control 2 …
24079 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24082 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24090 …__IO uint32_t GPIO_223_PIN_CONTROL_2; /*!< (@ 0x4008174C) GPIO 223 Pin Control 2 …
24093 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24096 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24104 …__IO uint32_t GPIO_224_PIN_CONTROL_2; /*!< (@ 0x40081750) GPIO 224 Pin Control 2 …
24107 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24110 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24118 …__IO uint32_t GPIO_225_PIN_CONTROL_2; /*!< (@ 0x40081754) GPIO 225 Pin Control 2 …
24121 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24124 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24132 …__IO uint32_t GPIO_226_PIN_CONTROL_2; /*!< (@ 0x40081758) GPIO 226 Pin Control 2 …
24135 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24138 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24146 …__IO uint32_t GPIO_227_PIN_CONTROL_2; /*!< (@ 0x4008175C) GPIO 227 Pin Control 2 …
24149 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24152 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24160 …__IO uint32_t GPIO_230_PIN_CONTROL_2; /*!< (@ 0x40081760) GPIO 230 Pin Control 2 …
24163 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24166 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24174 …__IO uint32_t GPIO_231_PIN_CONTROL_2; /*!< (@ 0x40081764) GPIO 231 Pin Control 2 …
24177 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24180 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24188 …__IO uint32_t GPIO_232_PIN_CONTROL_2; /*!< (@ 0x40081768) GPIO 232 Pin Control 2 …
24191 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24194 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24202 …__IO uint32_t GPIO_233_PIN_CONTROL_2; /*!< (@ 0x4008176C) GPIO 233 Pin Control 2 …
24205 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24208 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24216 …__IO uint32_t GPIO_234_PIN_CONTROL_2; /*!< (@ 0x40081770) GPIO 234 Pin Control 2 …
24219 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24222 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24230 …__IO uint32_t GPIO_235_PIN_CONTROL_2; /*!< (@ 0x40081774) GPIO 235 Pin Control 2 …
24233 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24236 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24245 …__IO uint32_t GPIO_240_PIN_CONTROL_2; /*!< (@ 0x40081780) GPIO 240 Pin Control 2 …
24248 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24251 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24259 …__IO uint32_t GPIO_241_PIN_CONTROL_2; /*!< (@ 0x40081784) GPIO 241 Pin Control 2 …
24262 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24265 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24273 …__IO uint32_t GPIO_242_PIN_CONTROL_2; /*!< (@ 0x40081788) GPIO 242 Pin Control 2 …
24276 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24279 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24287 …__IO uint32_t GPIO_243_PIN_CONTROL_2; /*!< (@ 0x4008178C) GPIO 243 Pin Control 2 …
24290 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24293 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24301 …__IO uint32_t GPIO_244_PIN_CONTROL_2; /*!< (@ 0x40081790) GPIO 244 Pin Control 2 …
24304 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24307 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24315 …__IO uint32_t GPIO_245_PIN_CONTROL_2; /*!< (@ 0x40081794) GPIO 245 Pin Control 2 …
24318 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24321 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24329 …__IO uint32_t GPIO_246_PIN_CONTROL_2; /*!< (@ 0x40081798) GPIO 246 Pin Control 2 …
24332 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24335 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24344 …__IO uint32_t GPIO_250_PIN_CONTROL_2; /*!< (@ 0x400817A0) GPIO 250 Pin Control 2 …
24347 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24350 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24359 …__IO uint32_t GPIO_253_PIN_CONTROL_2; /*!< (@ 0x400817AC) GPIO 253 Pin Control 2 …
24362 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24365 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24373 …__IO uint32_t GPIO_254_PIN_CONTROL_2; /*!< (@ 0x400817B0) GPIO 254 Pin Control 2 …
24376 …__IO uint32_t SLEW_RATE : 1; /*!< [0..0] This bit is used to select the slew rate…
24379 …__IO uint32_t DRIVE_STRENGTH: 2; /*!< [4..5] These bits are used to select the drive …
24401 …__IO uint16_t WDT_LOAD; /*!< (@ 0x40000000) Writing this field reloads t…
24406 …__IO uint16_t WDT_CONTROL; /*!< (@ 0x40000004) WDT Control Register …
24409 …__IO uint16_t WDT_ENABLE : 1; /*!< [0..0] WDT Block enabled …
24410 …__IO uint16_t WDT_STATUS : 1; /*!< [1..1] WDT_STATUS is set by hardware if the las…
24414 …__IO uint16_t HIBERNATION_TIMER0_STALL: 1; /*!< [2..2] This bit enables the WDT Stall function …
24418 …__IO uint16_t WEEK_TIMER_STALL: 1; /*!< [3..3] This bit enables the WDT Stall function …
24422 …__IO uint16_t JTAG_STALL : 1; /*!< [4..4] This bit enables the WDT Stall function …
24454 …__IO uint32_t COUNT; /*!< (@ 0x40000C00) This is the value of the Tim…
24456 …__IO uint32_t PRE_LOAD; /*!< (@ 0x40000C04) This is the value of the Tim…
24462 …__IO uint32_t STATUS; /*!< (@ 0x40000C08) This is the interrupt status t…
24466 …__IO uint32_t EVENT_INTERRUPT: 1; /*!< [0..0] This is the interrupt status that fires …
24477 …__IO uint32_t INT_EN; /*!< (@ 0x40000C0C) This is the interrupt enable f…
24481 …__IO uint32_t ENABLE : 1; /*!< [0..0] This is the interrupt enable for the sta…
24487 …__IO uint32_t CONTROL; /*!< (@ 0x40000C10) Timer Control Register …
24490 …__IO uint32_t ENABLE : 1; /*!< [0..0] This enables the block for operation. 1=…
24495 …__IO uint32_t COUNT_UP : 1; /*!< [2..2] This selects the counter direction. When…
24501 …__IO uint32_t AUTO_RESTART: 1; /*!< [3..3] This will select the action taken upon c…
24508 …__IO uint32_t SOFT_RESET : 1; /*!< [4..4] This is a soft reset. This is self clear…
24512 …__IO uint32_t START : 1; /*!< [5..5] This bit triggers the timer counter. The…
24518 …__IO uint32_t RELOAD : 1; /*!< [6..6] This bit reloads the counter without int…
24524 …__IO uint32_t HALT : 1; /*!< [7..7] This is a halt bit. This will halt the t…
24530 …__IO uint32_t PRE_SCALE : 16; /*!< [16..31] This is used to divide down the system…
24556 …__IO uint32_t TIMERX_CONTROL; /*!< (@ 0x40000D00) This bit reflects the current …
24560 …__IO uint32_t ENABLE : 1; /*!< [0..0] This bit is used to start and stop the t…
24567 …__IO uint32_t RESET : 1; /*!< [1..1] This bit stops the timer and resets the …
24576 …__IO uint32_t MODE : 2; /*!< [2..3] Timer Mode. 3=Measurement Mode; 2=One Sh…
24578 …__IO uint32_t INPOL : 1; /*!< [4..4] This bit selects the polarity of the TIN…
24580 …__IO uint32_t UPDN : 1; /*!< [5..5] In Event Mode, this bit selects the time…
24585 …__IO uint32_t TOUT_EN : 1; /*!< [6..6] This bit enables the TOUTx pin. 1=TOUTx …
24587 …__IO uint32_t RLOAD : 1; /*!< [7..7] Reload Control. This bit controls how th…
24594 …__IO uint32_t FILTER_BYPASS: 1; /*!< [8..8] This bit is used to enable or disable th…
24599 …__IO uint32_t PD : 1; /*!< [9..9] Power Down. 1=The timer is powered down …
24601 …__IO uint32_t TOUT_POLARITY: 1; /*!< [10..10] This bit determines the polarity of th…
24607 …__IO uint32_t SLEEP_ENABLE: 1; /*!< [11..11] This bit reflects the current state of…
24618 …__IO uint32_t PRELOAD; /*!< (@ 0x40000D04) This is the value of the Timer…
24624 …__IO uint32_t TCLK : 4; /*!< [0..3] Timer Clock Select. This field determine…
24627 …__IO uint32_t EDGE : 2; /*!< [5..6] This field selects which edge of the TIN…
24637 …__IO uint32_t EVENT : 1; /*!< [7..7] Event Select. This bit is used to select…
24641 …__IO uint32_t FCLK : 4; /*!< [8..11] Timer Clock Select. This field determin…
24648 …__IO uint32_t TIMERX_RELOAD; /*!< (@ 0x40000D08) This register is used in Timer…
24652 …__IO uint32_t TIMER_RELOAD: 16; /*!< [0..15] The Timer Reload register is used in Ti…
24666 …__IO uint32_t TIMERX_COUNT; /*!< (@ 0x40000D0C) This register returns the curr…
24689 …__IO uint32_t CAPTURE_COMPARE_TIMER_CONTROL; /*!< (@ 0x40001000) This register controls the cap…
24693 …__IO uint32_t ACTIVATE : 1; /*!< [0..0] This bit is used to start the capture an…
24695 …__IO uint32_t FREE_ENABLE: 1; /*!< [1..1] Free-Running Timer Enable. This bit is u…
24697 …__IO uint32_t FREE_RESET : 1; /*!< [2..2] Free Running Timer Reset. This bit stops…
24700 …__IO uint32_t TCLK : 3; /*!< [4..6] This 3-bit field sets the clock source f…
24703 …__IO uint32_t COMPARE_ENABLE0: 1; /*!< [8..8] Compare Enable for Compare 0 Register. …
24704 …__IO uint32_t COMPARE_ENABLE1: 1; /*!< [9..9] Compare Enable for Compare 1 Register. …
24706 …__IO uint32_t COMPARE_SET1: 1; /*!< [16..16] When read, returns the current value o…
24708 …__IO uint32_t COMPARE_SET0: 1; /*!< [17..17] When read, returns the current value o…
24711 …__IO uint32_t COMPARE_CLEAR1: 1; /*!< [24..24] When read, returns the current value o…
24713 …__IO uint32_t COMPARE_CLEAR0: 1; /*!< [25..25] When read, returns the current value o…
24719 …__IO uint32_t CAPTURE_CONTROL_0; /*!< (@ 0x40001004) This register is used to confi…
24723 …__IO uint32_t CAPTURE_EDGE0: 2; /*!< [0..1] This field selects the edge type that tr…
24725 …__IO uint32_t FILTER_BYP0: 1; /*!< [2..2] This bit enables bypassing the input noi…
24729 …__IO uint32_t FCLK_SEL0 : 3; /*!< [5..7] This 3-bit field sets the clock source f…
24731 …__IO uint32_t CAPTURE_EDGE1: 2; /*!< [8..9] This field selects the edge type that tr…
24733 …__IO uint32_t FILTER_BYP1: 1; /*!< [10..10] This bit enables bypassing the input n…
24737 …__IO uint32_t FCLK_SEL1 : 3; /*!< [13..15] This 3-bit field sets the clock source…
24739 …__IO uint32_t CAPTURE_EDGE2: 2; /*!< [16..17] This field selects the edge type that …
24742 …__IO uint32_t FILTER_BYP2: 1; /*!< [18..18] This bit enables bypassing the input n…
24746 …__IO uint32_t FCLK_SEL2 : 3; /*!< [21..23] This 3-bit field sets the clock source…
24748 …__IO uint32_t CAPTURE_EDGE3: 2; /*!< [24..25] This field selects the edge type that …
24751 …__IO uint32_t FILTER_BYP3: 1; /*!< [26..26] This bit enables bypassing the input n…
24755 …__IO uint32_t FCLK_SEL3 : 3; /*!< [29..31] This 3-bit field sets the clock source…
24761 …__IO uint32_t CAPTURE_CONTROL_1; /*!< (@ 0x40001008) This register is used to confi…
24765 …__IO uint32_t CAPTURE_EDGE4: 2; /*!< [0..1] This field selects the edge type that tr…
24767 …__IO uint32_t FILTER_BYP4: 1; /*!< [2..2] This bit enables bypassing the input noi…
24771 …__IO uint32_t FCLK_SEL4 : 3; /*!< [5..7] This 3-bit field sets the clock source f…
24773 …__IO uint32_t CAPTURE_EDGE5: 2; /*!< [8..9] This field selects the edge type that tr…
24775 …__IO uint32_t FILTER_BYP5: 1; /*!< [10..10] This bit enables bypassing the input n…
24779 …__IO uint32_t FCLK_SEL5 : 3; /*!< [13..15] This 3-bit field sets the clock source…
24785 …__IO uint32_t FREE_RUNNING_TIMER; /*!< (@ 0x4000100C) This register contains the cur…
24789 …__IO uint32_t FREE_RUNNING_TIMER: 32; /*!< [0..31] This register contains the current valu…
24795 …__IO uint32_t CAPTURE_0; /*!< (@ 0x40001010) This register saves the value …
24799 …__IO uint32_t CAPTURE_0 : 32; /*!< [0..31] This register saves the value copied fr…
24805 …__IO uint32_t CAPTURE_1; /*!< (@ 0x40001014) This register saves the value …
24809 …__IO uint32_t CAPTURE_1 : 32; /*!< [0..31] This register saves the value copied fr…
24815 …__IO uint32_t CAPTURE_2; /*!< (@ 0x40001018) This register saves the value …
24819 …__IO uint32_t CAPTURE_2 : 32; /*!< [0..31] This register saves the value copied fr…
24825 …__IO uint32_t CAPTURE_3; /*!< (@ 0x4000101C) This register saves the value …
24829 …__IO uint32_t CAPTURE_3 : 32; /*!< [0..31] This register saves the value copied fr…
24835 …__IO uint32_t CAPTURE_4; /*!< (@ 0x40001020) This register saves the value …
24839 …__IO uint32_t CAPTURE_4 : 32; /*!< [0..31] This register saves the value copied fr…
24845 …__IO uint32_t CAPTURE_5; /*!< (@ 0x40001024) This register saves the value …
24849 …__IO uint32_t CAPTURE_5 : 32; /*!< [0..31] This register saves the value copied fr…
24855 …__IO uint32_t COMPARE_0; /*!< (@ 0x40001028) A COMPARE 0 interrupt is gener…
24859 …__IO uint32_t COMPARE_0 : 32; /*!< [0..31] A COMPARE 0 interrupt is generated when…
24865 …__IO uint32_t COMPARE_1; /*!< (@ 0x4000102C) A COMPARE 1 interrupt is gener…
24869 …__IO uint32_t COMPARE_1 : 32; /*!< [0..31] A COMPARE 1 interrupt is generated when…
24888 …__IO uint16_t HT_PRELOAD; /*!< (@ 0x40009800) [15:0] This register is used…
24893 …__IO uint16_t HT_CONTROL; /*!< (@ 0x40009804) HTimer Control Register …
24896 …__IO uint16_t CTRL : 1; /*!< [0..0] 1= The Hibernation Timer has a resolutio…
24923 …__IO uint32_t RTOS_TIMER_COUNT; /*!< (@ 0x40007400) RTOS Timer Count Register. …
24926 …__IO uint32_t COUNTER : 32; /*!< [0..31] This register contains the current valu…
24936 …__IO uint32_t RTOS_TIMER_PRELOAD; /*!< (@ 0x40007404) RTOS Timer Preload Register …
24939 …__IO uint32_t PRE_LOAD : 32; /*!< [0..31] The this register is loaded into the RT…
24953 …__IO uint32_t RTOS_TIMER_CONTROL; /*!< (@ 0x40007408) RTOS Timer Control Register …
24956 __IO uint32_t BLOCK_ENABLE: 1; /*!< [0..0] 1=RTOS timer counter is enabled
24959 …__IO uint32_t AUTO_RELOAD: 1; /*!< [1..1] 1=The the RTOS Timer Preload Register is…
24964 …__IO uint32_t TIMER_START: 1; /*!< [2..2] Writing a 1 to this bit will load the ti…
24973 …__IO uint32_t EXT_HARDWARE_HALT_EN: 1; /*!< [3..3] 1=The timer counter is halted when the e…
24976 …__IO uint32_t FIRMWARE_TIMER_HALT: 1; /*!< [4..4] 1=The timer counter is halted. If the co…
25015 …__IO uint8_t SEC; /*!< (@ 0x400F5000) Seconds Register …
25016 …__IO uint8_t SEC_ALARM; /*!< (@ 0x400F5001) Seconds Alarm Register …
25017 …__IO uint8_t MIN; /*!< (@ 0x400F5002) Minutes Register …
25018 …__IO uint8_t MIN_ALARM; /*!< (@ 0x400F5003) Minutes Alarm Register …
25019 …__IO uint8_t HR; /*!< (@ 0x400F5004) Hours Register …
25020 …__IO uint8_t HR_ALARM; /*!< (@ 0x400F5005) Hours Alarm Register …
25021 …__IO uint8_t DAY_WEEK; /*!< (@ 0x400F5006) Day of Week Register …
25022 …__IO uint8_t DAY_MONTH; /*!< (@ 0x400F5007) Day of Month Register …
25023 …__IO uint8_t MONTH; /*!< (@ 0x400F5008) Month Register …
25024 …__IO uint8_t YEAR; /*!< (@ 0x400F5009) Year Register …
25025 …__IO uint8_t REG_A; /*!< (@ 0x400F500A) Register A …
25026 …__IO uint8_t REG_B; /*!< (@ 0x400F500B) Register B …
25027 …__IO uint8_t REG_C; /*!< (@ 0x400F500C) Register C …
25028 …__IO uint8_t REG_D; /*!< (@ 0x400F500D) Register D …
25032 …__IO uint32_t CONTROL; /*!< (@ 0x400F5010) RTC Control Register …
25035 …__IO uint32_t BLOCK_ENABLE: 1; /*!< [0..0] BLOCK_ENABLE This bit must be '1' in ord…
25039 …__IO uint32_t SOFT_RESET : 1; /*!< [1..1] SOFT_RESET A '1' written to this bit pos…
25045 …__IO uint32_t TEST : 1; /*!< [2..2] TEST …
25046 …__IO uint32_t ALARM_ENABLE: 1; /*!< [3..3] ALARM_ENABLE 1=Enables the Alarm feature…
25050 …__IO uint32_t WEEK_ALARM; /*!< (@ 0x400F5014) Week Alarm Register[7:0] - A…
25057 …__IO uint32_t DAYLIGHT_SAVINGS_FORWARD; /*!< (@ 0x400F5018) Daylight Savings Forward Regis…
25060 …__IO uint32_t DST_MONTH : 8; /*!< [0..7] This field matches the Month Register. …
25061 …__IO uint32_t DST_DAY_OF_WEEK: 3; /*!< [8..10] This field matches the Day of Week Regi…
25064 …__IO uint32_t DST_WEEK : 3; /*!< [16..18] 5=Last week of month, 4 =Fourth week o…
25068 …__IO uint32_t DST_HOUR : 7; /*!< [24..30] This field holds the matching value fo…
25072 …__IO uint32_t DST_AM_PM : 1; /*!< [31..31] This bit selects AM vs. PM, to match b…
25080 …__IO uint32_t DAYLIGHT_SAVINGS_BACKWARD; /*!< (@ 0x400F501C) Daylight Savings Backward Regi…
25083 …__IO uint32_t DST_MONTH : 8; /*!< [0..7] This field matches the Month Register. …
25084 …__IO uint32_t DST_DAY_OF_WEEK: 3; /*!< [8..10] This field matches the Day of Week Regi…
25087 …__IO uint32_t DST_WEEK : 3; /*!< [16..18] 5=Last week of month, 4 =Fourth week o…
25091 …__IO uint32_t DST_HOUR : 7; /*!< [24..30] This field holds the matching value fo…
25095 …__IO uint32_t DST_AM_PM : 1; /*!< [31..31] This bit selects AM vs. PM, to match b…
25117 …__IO uint32_t CONTROL_REGISTER; /*!< (@ 0x4000AC80) Control Register …
25120 …__IO uint32_t WT_ENABLE : 1; /*!< [0..0] The WT_ENABLE bit is used to start and s…
25129 …__IO uint32_t POWERUP_EN : 1; /*!< [6..6] This bit controls the state of the Power…
25138 …__IO uint32_t WEEK_ALARM_COUNTER; /*!< (@ 0x4000AC84) Week Alarm Counter Register …
25141 …__IO uint32_t WEEK_COUNTER: 28; /*!< [0..27] While the WT_ENABLE bit is 1, this regi…
25150 …__IO uint32_t WEEK_TIMER_COMPARE; /*!< (@ 0x4000AC88) Week Timer Compare Register …
25153 …__IO uint32_t WEEK_COMPARE: 28; /*!< [0..27] A Week Alarm Interrupt and a Week Alarm…
25162 …__IO uint32_t CLOCK_DIVIDER; /*!< (@ 0x4000AC8C) Clock Divider Register …
25171 …__IO uint32_t SUB_SECOND_INT_SELECT; /*!< (@ 0x4000AC90) Sub-Second Programmable Interr…
25175 …__IO uint32_t SPISR : 4; /*!< [0..3] This field determines the rate at which …
25184 …__IO uint32_t SUBWEEK_TIMER_POWERUP_EVENT_STATUS: 1;/*!< [0..0] This bit is set to 1 when the Su…
25189 …__IO uint32_t WEEK_TIMER_POWERUP_EVENT_STATUS: 1;/*!< [1..1] This bit is set to 1 when the Week …
25197 …__IO uint32_t TEST0 : 1; /*!< [5..5] Test …
25198 …__IO uint32_t AUTO_RELOAD: 1; /*!< [6..6] 1= No reload occurs when the Sub-Week Co…
25201 …__IO uint32_t SUBWEEK_TICK: 3; /*!< [7..9] This field selects the clock source for …
25210 …__IO uint32_t SUBWEEK_COUNTER_LOAD: 9; /*!< [0..8] Writes with a non-zero value to this fie…
25216 …__IO uint32_t SUBWEEK_COUNTER_STATUS: 9; /*!< [16..24] Reads of this register return the curr…
25222 …__IO uint32_t BGPO_DATA; /*!< (@ 0x4000AC9C) BGPO Data Register …
25225 …__IO uint32_t BGPO : 10; /*!< [0..9] Battery powered General Purpose Output. …
25239 …__IO uint32_t BGPO_POWER; /*!< (@ 0x4000ACA0) BGPO Power Register …
25243 …__IO uint32_t BGPO_POWER : 5; /*!< [1..5] Battery powered General Purpose Output p…
25258 …__IO uint32_t BGPO_RESET; /*!< (@ 0x4000ACA4) BGPO Reset Register …
25261 …__IO uint32_t BGPO_RESET : 10; /*!< [0..9] Battery powered General Purpose Output r…
25283 …__IO uint32_t TACH_CONTROL; /*!< (@ 0x40006000) TACHx Control Register …
25286 …__IO uint32_t TACH_OUT_OF_LIMIT_ENABLE: 1; /*!< [0..0] TACH_OUT_OF_LIMIT_ENABLE This bit is use…
25291 …__IO uint32_t TACH_ENABLE: 1; /*!< [1..1] TACH_ENABLE 1= TACH Monitoring enabled, …
25294 …__IO uint32_t FILTER_ENABLE: 1; /*!< [8..8] FILTER_ENABLE This filter is used to rem…
25302 __IO uint32_t TACH_READING_MODE_SELECT: 1; /*!< [10..10] TACH_READING_MODE_SELECT
25308 …__IO uint32_t TACH_EDGES : 2; /*!< [11..12] TACH_EDGES A Tach signal is a square w…
25319 …__IO uint32_t COUNT_READY_INT_EN: 1; /*!< [14..14] COUNT_READY_INT_EN 1=Enable Count Read…
25322 …__IO uint32_t TACH_INPUT_INT_EN: 1; /*!< [15..15] TACH_INPUT_INT_EN 1=Enable Tach Input …
25333 …__IO uint32_t TACHX_STATUS; /*!< (@ 0x40006004) TACHx Status Register …
25336 …__IO uint32_t TACH_OUT_OF_LIMIT_STATUS: 1; /*!< [0..0] TACH_OUT_OF_LIMIT_STATUS 1=Tach is outsi…
25340 …__IO uint32_t TOGGLE_STATUS: 1; /*!< [2..2] TOGGLE_STATUS 1=Tach Input changed state…
25343 …__IO uint32_t COUNT_READY_STATUS: 1; /*!< [3..3] COUNT_READY_STATUS 1=Reading ready, 0=Re…
25349 …__IO uint32_t TACHX_HIGH_LIMIT; /*!< (@ 0x40006008) TACH HIGH LIMIT Register …
25352 …__IO uint32_t TACH_HIGH_LIMIT: 16; /*!< [0..15] This value is compared with the value i…
25364 …__IO uint32_t TACHX_LOW_LIMIT; /*!< (@ 0x4000600C) TACHx Low Limit Register …
25367 …__IO uint32_t TACH_LOW_LIMIT: 16; /*!< [0..15] This value is compared with the value i…
25393 …__IO uint32_t COUNTER_ON_TIME; /*!< (@ 0x40005800) This field determines both t…
25400 …__IO uint32_t COUNTER_OFF_TIME; /*!< (@ 0x40005804) This field determine both th…
25409 …__IO uint32_t CONFIG; /*!< (@ 0x40005808) PWMx CONFIGURATION REGISTER …
25412 …__IO uint32_t PWM_ENABLE : 1; /*!< [0..0] When the PWM_ENABLE is set to 0 the inte…
25421 …__IO uint32_t CLK_SELECT : 1; /*!< [1..1] This bit determines the clock source use…
25425 …__IO uint32_t INVERT : 1; /*!< [2..2] 1= PWM_OUTPUT ON State is active low; 0=…
25427 …__IO uint32_t CLK_PRE_DIVIDER: 4; /*!< [3..6] The Clock source for the 16-bit down cou…
25451 …__IO uint8_t WRITE_DATA; /*!< (@ 0x40006400) The Write Data Register prov…
25454 …__IO uint8_t READ_DATA; /*!< (@ 0x40006404) The Read Data Register provi…
25459 …__IO uint8_t CONTROL; /*!< (@ 0x40006408) Control Register …
25462 …__IO uint8_t PD : 1; /*!< [0..0] PD (Power Down) along with RST controls …
25465 …__IO uint8_t RST : 1; /*!< [3..3] RST indicates that the PECI Core should …
25467 …__IO uint8_t FRST : 1; /*!< [5..5] FRST is the FIFO Reset bit. …
25468 …__IO uint8_t TXEN : 1; /*!< [6..6] TXEN is the Transmit Enable bit. …
25469 …__IO uint8_t MIEN : 1; /*!< [7..7] MIEN is the Master Interrupt Enable …
25475 …__IO uint8_t STATUS1; /*!< (@ 0x4000640C) Status Register 1 …
25478 …__IO uint8_t BOF : 1; /*!< [0..0] BOF (Beginning of Frame) is asserted whe…
25480 …__IO uint8_t PEOF : 1; /*!< [1..1] PEOF (End of Frame) is asserted followi…
25486 …__IO uint8_t RDYLO : 1; /*!< [4..4] RDYLO is asserted '1' on the falling edg…
25488 …__IO uint8_t RDYHI : 1; /*!< [5..5] RDYHI is asserted '1' on the rising edge…
25518 …__IO uint8_t ERROR; /*!< (@ 0x40006414) Error Register …
25521 …__IO uint8_t FERR : 1; /*!< [0..0] FERR (Frame Check Sequence Error). (R/WC…
25522 …__IO uint8_t BERR : 1; /*!< [1..1] BERR (Bus Error). Bus contention has bee…
25526 …__IO uint8_t REQERR : 1; /*!< [3..3] REQERR is asserted if PEC_AVAILABLE (REA…
25529 …__IO uint8_t WROV : 1; /*!< [4..4] WROV (Write Overrun). (R/WC) …
25530 …__IO uint8_t WRUN : 1; /*!< [5..5] WRUN (Write Underrun). (R/WC) …
25531 …__IO uint8_t RDOV : 1; /*!< [6..6] RDOV (Read Overrun). RDOV indicates that…
25533 …__IO uint8_t CLKERR : 1; /*!< [7..7] CLKERR indicates that the READY signal f…
25541 …__IO uint8_t INT_EN1; /*!< (@ 0x40006418) Interrupt Enable 1 Register …
25544 …__IO uint8_t BIEN : 1; /*!< [0..0] When the BIEN bit is asserted '1' the BO…
25546 …__IO uint8_t EIEN : 1; /*!< [1..1] When the EIEN bit is asserted '1' the EO…
25548 …__IO uint8_t EREN : 1; /*!< [2..2] When the EREN bit is asserted '1' the ER…
25551 …__IO uint8_t RLEN : 1; /*!< [4..4] When the RLEN bit is asserted '1' the RD…
25553 …__IO uint8_t RHEN : 1; /*!< [5..5] When the RHEN bit is asserted '1' the RD…
25560 …__IO uint8_t INT_EN2; /*!< (@ 0x4000641C) Interrupt Enable 2 Register …
25564 …__IO uint8_t ENWFE : 1; /*!< [1..1] When the ENWFE bit is asserted '1' the W…
25566 …__IO uint8_t ENRFF : 1; /*!< [2..2] When the ENRFF bit is asserted '1' the R…
25571 …__IO uint8_t OBT1; /*!< (@ 0x40006420) Optimal Bit Time Register (L…
25573 …__IO uint8_t OBT2; /*!< (@ 0x40006424) Optimal Bit Time Register (H…
25575 …__IO uint32_t ID; /*!< (@ 0x40006440) Block ID Register …
25576 …__IO uint32_t REV; /*!< (@ 0x40006444) Revision Register …
25592 …__IO uint32_t CONTROL; /*!< (@ 0x40007C00) The ADC Control Register is us…
25596 …__IO uint32_t ACTIVATE : 1; /*!< [0..0] 0: The ADC is disabled and placed in its…
25598 …__IO uint32_t START_SINGLE: 1; /*!< [1..1] (START_SINGLE) 0: The ADC Single Mode is…
25601 …__IO uint32_t START_REPEAT: 1; /*!< [2..2] 0: The ADC Repeat Mode is disabled. 1: T…
25603 …__IO uint32_t POWER_SAVER_DIS: 1; /*!< [3..3] 0: Power saving feature is enabled. 1: P…
25605 …__IO uint32_t SOFT_RESET : 1; /*!< [4..4] (SOFT_RESET) 1: writing one causes a res…
25609 …__IO uint32_t REPEAT_DONE_STAT: 1; /*!< [6..6] 0: ADC repeat-sample conversion is not c…
25611 …__IO uint32_t SINGLE_DONE_STAT: 1; /*!< [7..7] 0: ADC single-sample conversion is not c…
25617 …__IO uint32_t DELAY; /*!< (@ 0x40007C04) The ADC Delay register determi…
25623 …__IO uint32_t START_DELAY: 16; /*!< [0..15] This field determines the starting dela…
25625 …__IO uint32_t REPEAT_DELAY: 16; /*!< [16..31] This field determines the interval bet…
25631 …__IO uint32_t STATUS; /*!< (@ 0x40007C08) The ADC Status Register indica…
25639 …__IO uint32_t ADC_CH_STATUS: 16; /*!< [0..15] All bits are cleared by being written w…
25651 …__IO uint32_t SINGLE_EN; /*!< (@ 0x40007C0C) The ADC Single Register is use…
25661 …__IO uint32_t SINGLE_EN : 16; /*!< [0..15] Each bit in this field enables the corr…
25671 …__IO uint32_t REPEAT; /*!< (@ 0x40007C10) The ADC Repeat Register is use…
25676 …__IO uint32_t RPT_EN : 16; /*!< [0..15] Each bit in this field enables the corr…
25683 …__IO uint32_t ADC_CHANNEL_READING[16]; /*!< (@ 0x40007C14) All 16 ADC channels return t…
25704 …__IO uint16_t FAN_SETTING; /*!< (@ 0x4000A000) The Fan Driver Setting used to…
25709 …__IO uint16_t FAN_SETTING: 10; /*!< [6..15] The Fan Driver Setting used to control …
25715 …__IO uint16_t CONFIGURATION; /*!< (@ 0x4000A002) The Fan Configuration Register…
25720 …__IO uint16_t UPDATE : 3; /*!< [0..2] Determines the base time between fan dri…
25737 …__IO uint16_t EDGES : 2; /*!< [3..4] Determines the minimum number of edges t…
25747 …__IO uint16_t RANGE : 2; /*!< [5..6] Adjusts the range of reported and progra…
25755 …__IO uint16_t EN_ALGO : 1; /*!< [7..7] Enables the RPM based Fan Control Algori…
25763 …__IO uint16_t POLARITY : 1; /*!< [9..9] Determines the polarity of the PWM drive…
25774 …__IO uint16_t ERR_RNG : 2; /*!< [10..11] Control some of the advanced options t…
25783 …__IO uint16_t DER_OPT : 2; /*!< [12..13] Control some of the advanced options t…
25787 …__IO uint16_t DIS_GLITCH : 1; /*!< [14..14] Disables the low pass glitch filter th…
25791 …__IO uint16_t EN_RRC : 1; /*!< [15..15] Enables the ramp rate control circuitr…
25804 …__IO uint8_t PWM_DIVIDE; /*!< (@ 0x4000A004) PWM Divide …
25807 …__IO uint8_t PWM_DIVIDE : 8; /*!< [0..7] The PWM Divide value determines the fina…
25814 …__IO uint8_t GAIN; /*!< (@ 0x4000A005) Gain Register stores the gain …
25819 __IO uint8_t GAINP : 2; /*!< [0..1] The proportional gain term.
25825 __IO uint8_t GAINI : 2; /*!< [2..3] The integral gain term.
25831 __IO uint8_t GAIND : 2; /*!< [4..5] The derivative gain term.
25841 …__IO uint8_t SPIN_UP_CONFIGURATION; /*!< (@ 0x4000A006) The Fan Spin Up Configuration …
25845 …__IO uint8_t SPINUP_TIME: 2; /*!< [0..1] Determines the maximum Spin Time that th…
25855 …__IO uint8_t SPIN_LVL : 3; /*!< [2..4] Determines the final drive level that is…
25865 …__IO uint8_t NOKICK : 1; /*!< [5..5] Determines if the Spin Up Routine will d…
25875 …__IO uint8_t DRIVE_FAIL_CNT: 2; /*!< [6..7] Determines how many update cycles are us…
25887 …__IO uint8_t FAN_STEP; /*!< (@ 0x4000A007) FAN_STEP The Fan Step value re…
25891 …__IO uint8_t FAN_STEP : 8; /*!< [0..7] The Fan Step value represents the maximu…
25905 …__IO uint8_t MINIMUM_DRIVE; /*!< (@ 0x4000A008) the minimum drive setting for …
25909 …__IO uint8_t MIN_DRIVE : 8; /*!< [0..7] The minimum drive setting. …
25914 …__IO uint8_t VALID_TACH_COUNT; /*!< (@ 0x4000A009) The maximum TACH Reading Regis…
25918 …__IO uint8_t VALID_TACH_CNT: 8; /*!< [0..7] The maximum TACH Reading Register value …
25924 …__IO uint16_t FAN_DRIVE_FAIL_BAND; /*!< (@ 0x4000A00A) The number of Tach counts used…
25929 …__IO uint16_t FAN_DRIVE_FAIL_BAND: 13; /*!< [3..15] The number of Tach counts used by the F…
25935 …__IO uint16_t TACH_TARGET; /*!< (@ 0x4000A00C) The target tachometer value. …
25939 …__IO uint16_t TACH_TARGET: 13; /*!< [3..15] The target tachometer value. …
25944 …__IO uint16_t TACH_READING; /*!< (@ 0x4000A00E) [15:3] The current tachometer …
25954 …__IO uint8_t DRIVER_BASE_FREQUENCY; /*!< (@ 0x4000A010) [1:0] Determines the frequency…
25958 …__IO uint8_t PWM_BASE : 2; /*!< [0..1] Determines the frequency range of the PW…
25969 …__IO uint8_t STATUS; /*!< (@ 0x4000A011) The bits in this register are …
25973 …__IO uint8_t FAN_STALL : 1; /*!< [0..0] The bit Indicates that the tachometer me…
25977 …__IO uint8_t FAN_SPIN : 1; /*!< [1..1] The bit Indicates that the Spin up Routi…
25985 …__IO uint8_t DRIVE_FAIL : 1; /*!< [5..5] The bit Indicates that the RPM-based Fan…
26012 …__IO uint32_t CONFIG; /*!< (@ 0x4000B800) LED Configuration …
26015 __IO uint32_t CONTROL : 2; /*!< [0..1] CONTROL 3=PWM is always on
26020 …__IO uint32_t CLOCK_SOURCE: 1; /*!< [2..2] 1=Clock source is the 48 MHz clock, 0=Cl…
26022 …__IO uint32_t SYNCHRONIZE: 1; /*!< [3..3] SYNCHRONIZE When this bit is '1', all co…
26027 …__IO uint32_t PWM_SIZE : 2; /*!< [4..5] PWM_SIZE This bit controls the behavior …
26032 …__IO uint32_t ENABLE_UPDATE: 1; /*!< [6..6] ENABLE_UPDATE This bit is set to 1 when …
26040 …__IO uint32_t WDT_RELOAD : 8; /*!< [8..15] WDT_RELOAD The PWM Watchdog Timer count…
26043 …__IO uint32_t SYMMETRY : 1; /*!< [16..16] SYMMETRY 1=The rising and falling ramp…
26051 …__IO uint32_t LIMITS; /*!< (@ 0x4000B804) LED Limits This register may b…
26059 …__IO uint32_t MINIMUM : 8; /*!< [0..7] In breathing mode, when the current duty…
26065 …__IO uint32_t MAXIMUM : 8; /*!< [8..15] In breathing mode, when the current dut…
26074 …__IO uint32_t DELAY; /*!< (@ 0x4000B808) LED Delay …
26077 …__IO uint32_t LOW_PULSE : 12; /*!< [0..11] The number of PWM periods to wait befor…
26080 …__IO uint32_t HIGH_PULSE : 12; /*!< [12..23] In breathing mode, the number of PWM p…
26088 …__IO uint32_t UPDATE_STEPSIZE; /*!< (@ 0x4000B80C) This register has eight segmen…
26099 …__IO uint32_t STEP0 : 4; /*!< [0..3] Amount the current duty cycle is adjuste…
26102 …__IO uint32_t STEP1 : 4; /*!< [4..7] Amount the current duty cycle is adjuste…
26105 …__IO uint32_t STEP2 : 4; /*!< [8..11] Amount the current duty cycle is adjust…
26108 …__IO uint32_t STEP3 : 4; /*!< [12..15] Amount the current duty cycle is adjus…
26111 …__IO uint32_t STEP4 : 4; /*!< [16..19] Amount the current duty cycle is adjus…
26114 …__IO uint32_t STEP5 : 4; /*!< [20..23] Amount the current duty cycle is adjus…
26116 …__IO uint32_t STEP6 : 4; /*!< [24..27] Amount the current duty cycle is adjus…
26119 …__IO uint32_t STEP7 : 4; /*!< [28..31] Amount the current duty cycle is adjus…
26126 …__IO uint32_t UPDATE_INTERVAL; /*!< (@ 0x4000B810) LED Update Interval …
26129 …__IO uint32_t INTERVAL0 : 4; /*!< [0..3] The number of PWM periods between update…
26131 …__IO uint32_t INTERVAL1 : 4; /*!< [4..7] The number of PWM periods between update…
26133 …__IO uint32_t INTERVAL2 : 4; /*!< [8..11] The number of PWM periods between updat…
26135 …__IO uint32_t INTERVAL3 : 4; /*!< [12..15] The number of PWM periods between upda…
26137 …__IO uint32_t INTERVAL4 : 4; /*!< [16..19] The number of PWM periods between upda…
26139 …__IO uint32_t INTERVAL5 : 4; /*!< [20..23] The number of PWM periods between upda…
26141 …__IO uint32_t INTERVAL6 : 4; /*!< [24..27] The number of PWM periods between upda…
26143 …__IO uint32_t INTERVAL7 : 4; /*!< [28..31] The number of PWM periods between upda…
26149 …__IO uint32_t LED_OUTPUT_DELAY; /*!< (@ 0x4000B814) LED Output Delay …
26152 …__IO uint32_t OUTPUT_DELAY: 8; /*!< [0..7] The delay, in counts of the clock define…
26174 …__IO uint32_t RC_ID_CONTROL; /*!< (@ 0x40001400) RC_ID Control Register …
26177 …__IO uint32_t DONE : 1; /*!< [0..0] This bit is cleared to 0 when the RC_ID …
26180 …__IO uint32_t TC : 1; /*!< [1..1] This bit is cleared to 0 when the RC_ID …
26183 …__IO uint32_t CY_ER : 1; /*!< [2..2] This bit is 1 if an RC_ID measurement en…
26188 …__IO uint32_t START : 1; /*!< [6..6] Setting this bit to 1 initiates the Disc…
26190 …__IO uint32_t ENABLE : 1; /*!< [7..7] Clearing the bit to 0 causes the RC_ID i…
26195 …__IO uint32_t CLOCK_SET : 2; /*!< [8..9] This field selects the frequency of the …
26202 …__IO uint32_t RC_ID_DATA; /*!< (@ 0x40001404) Reads of this register provide…
26227 …__IO uint32_t KSO_CONTROL; /*!< (@ 0x40009C04) KSO Select and control …
26230 …__IO uint32_t SELECT : 5; /*!< [0..4] This field selects a KSO line (00000b = …
26233 …__IO uint32_t ALL : 1; /*!< [5..5] 0=When key scan is enabled, KSO output c…
26236 …__IO uint32_t KSEN : 1; /*!< [6..6] 0= Keyboard scan enabled, 1= Keyboard sc…
26238 …__IO uint32_t INVERT : 1; /*!< [7..7] 0= KSO[x] driven low when selected, 1= K…
26244 …__IO uint32_t KSI_STATUS; /*!< (@ 0x40009C0C) [7:0] Each bit in this field…
26251 …__IO uint32_t KSI_INT_EN; /*!< (@ 0x40009C10) [7:0] Each bit in KSI_INT_EN…
26255 …__IO uint32_t EXTENDED_CONTROL; /*!< (@ 0x40009C14) [0:0] PREDRIVE_ENABLE enable…
26312 …__IO uint32_t ACK : 1; /*!< [0..0] The Acknowledge bit (ACK) must normally be…
26320 …__IO uint32_t STO : 1; /*!< [1..1] See STA description …
26321 …__IO uint32_t STA : 1; /*!< [2..2] The STA and STO bits control the generatio…
26325 …__IO uint32_t ENI : 1; /*!< [3..3] Enable Interrupt bit (ENI) controls the In…
26328 …__IO uint32_t ESO : 1; /*!< [6..6] The Enable Serial Output bit (ESO) enables…
26330 …__IO uint32_t PIN : 1; /*!< [7..7] The Pending Interrupt Not (PIN) bit serves…
26340 __IO uint32_t OWN; /*!< (@ 0x40004004) Own Address Register
26347 …__IO uint32_t OWN_ADDRESS_1: 7; /*!< [0..6] The Own Address 1 bits configure one of …
26351 …__IO uint32_t OWN_ADDRESS_2: 7; /*!< [8..14] The Own Address 2 bits configure one of…
26356 …__IO uint8_t DATA_REG; /*!< (@ 0x40004008) This register holds the data…
26361 …__IO uint32_t MASTER_COMMAND; /*!< (@ 0x4000400C) SMBus Master Command Register …
26364 …__IO uint32_t MRUN : 1; /*!< [0..0] While this bit is 1, transfer bytes over…
26368 …__IO uint32_t MPROCEED : 1; /*!< [1..1] When this bit is 0, the Master State Mac…
26373 …__IO uint32_t START0 : 1; /*!< [8..8] If this bit is 1, send a Start bit on th…
26376 …__IO uint32_t STARTN : 1; /*!< [9..9] If this bit is 1, send a Start bit just …
26378 …__IO uint32_t STOP : 1; /*!< [10..10] If this bit is 1, send a Stop bit afte…
26380 …__IO uint32_t PEC_TERM : 1; /*!< [11..11] If this bit is 1, a copy of the PEC re…
26383 …__IO uint32_t READM : 1; /*!< [12..12] If this bit is 1, then the ReadCount f…
26387 …__IO uint32_t READ_PEC : 1; /*!< [13..13] If this bit is 0, reading from the SMB…
26391 …__IO uint32_t WRITE_COUNT: 8; /*!< [16..23] This field is a count of the number of…
26395 …__IO uint32_t READ_COUNT : 8; /*!< [24..31] This field is a count of the number of…
26406 …__IO uint32_t SLAVE_COMMAND; /*!< (@ 0x40004010) SMBus Slave Command Register …
26409 …__IO uint32_t SRUN : 1; /*!< [0..0] Setting this bit to 1 enables the Slave …
26411 …__IO uint32_t SPROCEED : 1; /*!< [1..1] When this bit is 0, the Slave State Mach…
26416 …__IO uint32_t SLAVE_PEC : 1; /*!< [2..2] If Slave_WriteCount is 0 and Slave_PEC i…
26421 …__IO uint32_t SLAVE_WRITECOUNT: 8; /*!< [8..15] This field is set to the number of byte…
26423 …__IO uint32_t SLAVE_READCOUNT: 8; /*!< [16..23] This field is decremented each time a …
26429 …__IO uint32_t PEC; /*!< (@ 0x40004014) Packet Error Check (PEC) Regis…
26432 …__IO uint32_t PEC : 8; /*!< [0..7] The SMBus Packet Error Check (PEC) byte.…
26437 …__IO uint32_t REPEATED_START_HOLD_TIME; /*!< (@ 0x40004018) Repeated Start Hold Time Regis…
26440 …__IO uint32_t RPT_START_HOLD_TIME: 8; /*!< [0..7] This is the value of the timing requirem…
26450 …__IO uint32_t COMPLETION; /*!< (@ 0x40004020) Completion Register …
26454 …__IO uint32_t DTEN : 1; /*!< [2..2] When DTEN is asserted ('1'), Device Time…
26457 …__IO uint32_t MCEN : 1; /*!< [3..3] When MCEN is asserted ('1'), Master Cumu…
26460 …__IO uint32_t SCEN : 1; /*!< [4..4] When SCEN is asserted ('1'), Slave Cumul…
26463 …__IO uint32_t BIDEN : 1; /*!< [5..5] When BIDEN is asserted ('1'), Bus Idle D…
26470 …__IO uint32_t DTO : 1; /*!< [8..8] DTO is the Device Time-out bit. (R/WC) …
26471 …__IO uint32_t MCTO : 1; /*!< [9..9] MCTO is the Master Cumulative Time-out b…
26472 …__IO uint32_t SCTO : 1; /*!< [10..10] SCTO is the Slave Cumulative Time-out …
26473 …__IO uint32_t CHDL : 1; /*!< [11..11] CHDL is the clock high time-out detect…
26474 …__IO uint32_t CHDH : 1; /*!< [12..12] CHDH is the bus idle time-out detect b…
26475 …__IO uint32_t BER : 1; /*!< [13..13] If this bit is 1, the BER bit in the S…
26478 …__IO uint32_t LAB : 1; /*!< [14..14] If this bit is 1, the LAB bit in the S…
26482 …__IO uint32_t SNAKR : 1; /*!< [16..16] If this bit is 1, the Slave state mach…
26490 …__IO uint32_t SPROT : 1; /*!< [19..19] If this bit is 1, the WriteCount[7:0] …
26494 …__IO uint32_t REPEAT_READ: 1; /*!< [20..20] If this bit is 1, the Slave State Mach…
26498 …__IO uint32_t REPEAT_WRITE: 1; /*!< [21..21] If this bit is 1, the Slave State Mach…
26503 …__IO uint32_t MNAKX : 1; /*!< [24..24] If this bit is 1, the Master state mac…
26511 …__IO uint32_t IDLE : 1; /*!< [29..29] This bit is set when the I2C bus becom…
26513 …__IO uint32_t MDONE : 1; /*!< [30..30] If this bit is 1, Master State machine…
26516 …__IO uint32_t SDONE : 1; /*!< [31..31] If this bit is 1, Slave State machine …
26523 …__IO uint32_t IDLE_SCALING; /*!< (@ 0x40004024) Idle Scaling Register …
26526 …__IO uint32_t FAIR_BUS_IDLE_MIN: 12; /*!< [0..11] This field defines the number of ticks …
26531 …__IO uint32_t FAIR_IDLE_DELAY: 12; /*!< [16..27] This field defines the number of ticks…
26539 …__IO uint32_t CONFIGURATION; /*!< (@ 0x40004028) Configuration Register …
26542 …__IO uint32_t PORT_SEL : 4; /*!< [0..3] The PORT SEL [3:0] bits determine which …
26545 …__IO uint32_t TCEN : 1; /*!< [4..4] When the Timing Check Enable bit (TCEN) …
26550 …__IO uint32_t TEST : 1; /*!< [6..6] Must be always written with 0. …
26551 …__IO uint32_t PECEN : 1; /*!< [7..7] When the PEC Enable bit (PECEN) is asser…
26553 …__IO uint32_t FEN : 1; /*!< [8..8] Input filtering enable. Input filtering …
26557 …__IO uint32_t RESET : 1; /*!< [9..9] When RESET is asserted ('1'), all logic …
26560 …__IO uint32_t ENAB : 1; /*!< [10..10] When ENAB (Enable) is not asserted ('0…
26564 …__IO uint32_t DSA : 1; /*!< [11..11] 0: Slave Address I2C Compatibility Mod…
26566 …__IO uint32_t FAIR : 1; /*!< [12..12] If this bit is 1, the MCTP Fairness pr…
26568 …__IO uint32_t TEST0 : 1; /*!< [13..13] Must be always written with 0. …
26588 …__IO uint32_t ENIDI : 1; /*!< [29..29] If this bit is 1, the Idle interrupt i…
26590 …__IO uint32_t ENMI : 1; /*!< [30..30] If this bit is 1, the Master Done inte…
26592 …__IO uint32_t ENSI : 1; /*!< [31..31] If this bit is 1, the Slave Done inter…
26598 …__IO uint32_t BUS_CLOCK; /*!< (@ 0x4000402C) Bus Clock Register …
26601 …__IO uint32_t LOW_PERIOD : 8; /*!< [0..7] This field defines the number of I2C Bau…
26603 …__IO uint32_t HIGH_PERIOD: 8; /*!< [8..15] This field defines the number of I2C Ba…
26612 …__IO uint8_t ID : 8; /*!< [0..7] Block ID. …
26621 …__IO uint8_t REVISION : 8; /*!< [0..7] Block Revision Number …
26627 …__IO uint32_t BIT_BANG_CONTROL; /*!< (@ 0x40004038) Bit-Bang Control Register …
26630 …__IO uint32_t BBEN : 1; /*!< [0..0] Bit-Bang Mode Enable. 0 - Bit Bang Mode …
26632 …__IO uint32_t CLDIR : 1; /*!< [1..1] Bit-Bang Clock Direction. The CLDIR bit …
26634 …__IO uint32_t DADIR : 1; /*!< [2..2] Bit-Bang Data Direction. The DADIR bit c…
26636 …__IO uint32_t BBCLK : 1; /*!< [3..3] Bit-Bang Clock. The BBCLK bit controls t…
26638 …__IO uint32_t BBDAT : 1; /*!< [4..4] Bit-Bang Data. The BBDAT bit controls th…
26651 …__IO uint8_t TEST : 8; /*!< [0..7] This register must not be written, or un…
26658 …__IO uint32_t DATA_TIMING; /*!< (@ 0x40004040) Data Timing Register …
26661 …__IO uint32_t DATA_HOLD : 8; /*!< [0..7] The Data Hold [7:0] timer determines the…
26663 …__IO uint32_t RESTART_SETUP: 8; /*!< [8..15] The Restart Setup [7:0] timer determine…
26666 …__IO uint32_t STOP_SETUP : 8; /*!< [16..23] The Stop Setup [7:0] timer determines …
26668 …__IO uint32_t FIRST_START_HOLD: 8; /*!< [24..31] This field determines the SCL hold tim…
26678 …__IO uint32_t TIME_OUT_SCALING; /*!< (@ 0x40004044) Time-Out Scaling Register …
26681 …__IO uint32_t CLOCK_HIGH_TIME_OUT: 8; /*!< [0..7] Clock High time out period = Clock High …
26683 …__IO uint32_t SLAVE_CUM_TIME_OUT: 8; /*!< [8..15] Slave Cumulative Time-Out duration = Sl…
26685 …__IO uint32_t MASTER_CUM_TIME_OUT: 8; /*!< [16..23] Master Cumulative Time-Out duration = …
26687 …__IO uint32_t BUS_IDLE_MIN: 8; /*!< [24..31] Bus Idle Minimum time = Bus Idle Min […
26693 …__IO uint32_t SLAVE_TRANSMIT_BUFFER; /*!< (@ 0x40004048) SMBus Slave Transmit Buffer Re…
26696 …__IO uint32_t SLAVE_TRANSMIT_BUFFER: 8; /*!< [0..7] SLAVE_TRANSMIT_BUFFER …
26701 …__IO uint32_t SLAVE_RECEIVE_BUFFER; /*!< (@ 0x4000404C) SMBus Slave Receive Buffer Reg…
26704 …__IO uint32_t SLAVE_RECEIVE_BUFFER: 8; /*!< [0..7] SLAVE_RECEIVE_BUFFER …
26709 …__IO uint32_t MASTER_TRANSMIT_BUFER; /*!< (@ 0x40004050) SMBus Master Transmit Buffer R…
26712 …__IO uint32_t MASTER_TRANSMIT_BUFFER: 8; /*!< [0..7] MASTER_TRANSMIT_BUFFER …
26717 …__IO uint32_t MASTER_RECEIVE_BUFFER; /*!< (@ 0x40004054) SMBus Master Receive Buffer Re…
26720 …__IO uint32_t MASTER_RECEIVE_BUFFER: 8; /*!< [0..7] MASTER_RECEIVE_BUFFER …
26726 …__IO uint32_t WAKE_STATUS; /*!< (@ 0x40004060) WAKE STATUS Register …
26729 …__IO uint32_t START_BIT_DETECTION: 1; /*!< [0..0] This bit is set to '1' when a START bit …
26736 …__IO uint32_t WAKE_ENABLE; /*!< (@ 0x40004064) WAKE ENABLE Register …
26739 …__IO uint32_t START_DETECT_INT_EN: 1; /*!< [0..0] Enable Start Bit Detection Interrupt. Th…
26760 …__IO uint32_t ENABLE; /*!< (@ 0x40009400) [0:0] 1=Enabled. The device …
26765 …__IO uint32_t CONTROL; /*!< (@ 0x40009404) SPI Control …
26768 __IO uint32_t LSBF : 1; /*!< [0..0] Least Significant Bit First
26771 __IO uint32_t BIOEN : 1; /*!< [1..1] Bidirectional Output Enable control.
26776 …__IO uint32_t SPDIN_SELECT: 2; /*!< [2..3] [3:2] 1xb=SPDIN1 and SPDIN2. Select this…
26780 …__IO uint32_t SOFT_RESET : 1; /*!< [4..4] Soft Reset is a self-clearing bit. Writi…
26784 __IO uint32_t AUTO_READ : 1; /*!< [5..5] Auto Read Enable.
26789 __IO uint32_t CE : 1; /*!< [6..6] SPI Chip Select Enable.
26808 …__IO uint32_t TX_DATA; /*!< (@ 0x4000940C) [7:0] A write to this regist…
26811 …__IO uint32_t RX_DATA; /*!< (@ 0x40009410) [7:0] This register is used …
26815 …__IO uint32_t CLOCK_Control; /*!< (@ 0x40009414) SPI Clock Control. This regist…
26819 …__IO uint32_t TCLKPH : 1; /*!< [0..0] 1=Valid data is clocked out on the first…
26827 …__IO uint32_t RCLKPH : 1; /*!< [1..1] 1=Valid data on SPDIN signal is expected…
26833 …__IO uint32_t CLKPOL : 1; /*!< [2..2] 1=The SPI_CLK signal is high when the in…
26838 …__IO uint32_t CLKSRC : 1; /*!< [4..4] 1=2MHz, 0=48 MHz Ring Oscillator …
26841 …__IO uint32_t CLOCK_GENERATOR; /*!< (@ 0x40009418) [5:0] PRELOAD SPI Clock Gene…
26860 …__IO uint32_t QMSPI_MODE; /*!< (@ 0x40005400) QMSPI Mode Register …
26863 …__IO uint32_t ACTIVATE : 1; /*!< [0..0] This bit is used to activate the QMSPI b…
26870 …__IO uint32_t CPOL : 1; /*!< [8..8] Polarity of the SPI clock line when ther…
26873 …__IO uint32_t CHPA_MOSI : 1; /*!< [9..9] Clock phase of the Master data out. Comm…
26882 …__IO uint32_t CHPA_MISO : 1; /*!< [10..10] Clock phase of the Master data in. Com…
26892 …__IO uint32_t CLOCK_DIVIDE: 9; /*!< [16..24] The SPI clock divide in number of syst…
26900 …__IO uint32_t QMSPI_CONTROL; /*!< (@ 0x40005404) QMSPI SPI Control …
26903 …__IO uint32_t INTERFACE_MODE: 2; /*!< [0..1] This field sets the transmission mode. I…
26908 …__IO uint32_t TX_TRANSFER_ENABLE: 2; /*!< [2..3] This field bit selects the transmit func…
26918 …__IO uint32_t TX_DMA_ENABLE: 2; /*!< [4..5] This bit enables DMA support for Transmi…
26928 …__IO uint32_t RX_TRANSFER_ENABLE: 1; /*!< [6..6] This bit enables the receive function of…
26932 …__IO uint32_t RX_DMA_ENABLE: 2; /*!< [7..8] This bit enables DMA support for Receive…
26942 …__IO uint32_t CLOSE_TRANSFER_ENABLE: 1; /*!< [9..9] This selects what action is taken at the…
26950 …__IO uint32_t TRANSFER_UNITS: 2; /*!< [10..11] 3=TRANSFER_LENGTH defined in units of …
26954 …__IO uint32_t DESCRIPTION_BUFFER_POINTER: 4;/*!< [12..15] This field selects the first buffer us…
26956 …__IO uint32_t DESCRIPTION_BUFFER_ENABLE: 1; /*!< [16..16] This enables the Description Buffers t…
26960 …__IO uint32_t TRANSFER_LENGTH: 15; /*!< [17..31] The length of the SPI transfer. The co…
26967 …__IO uint32_t QMSPI_EXECUTE; /*!< (@ 0x40005408) QMSPI Execute Register …
26987 …__IO uint32_t QMSPI_INTERFACE_CONTROL; /*!< (@ 0x4000540C) QMSPI Interface Control Regist…
26990 …__IO uint32_t WRITE_PROTECT_OUT_VALUE: 1; /*!< [0..0] This bit sets the value on the WRITE PRO…
26994 …__IO uint32_t WRITE_PROTECT_OUT_ENABLE: 1; /*!< [1..1] 1=WRITE PROTECT SPI Output Port is driven
26996 …__IO uint32_t HOLD_OUT_VALUE: 1; /*!< [2..2] This bit sets the value on the HOLD SPI …
26999 __IO uint32_t HOLD_OUT_ENABLE: 1; /*!< [3..3] 1=HOLD SPI Output Port is driven
27001 …__IO uint32_t PULLDOWN_ON_NOT_SELECTED: 1; /*!< [4..4] 1=Enable pull-down resistors on Receive …
27004 …__IO uint32_t PULLUP_ON_NOT_SELECTED: 1; /*!< [5..5] 1=Enable pull-up resistors on Receive pi…
27007 …__IO uint32_t PULLDOWN_ON_NOT_DRIVEN: 1; /*!< [6..6] 1=Enable pull-down resistors on Transmit…
27010 …__IO uint32_t PULLUP_ON_NOT_DRIVEN: 1; /*!< [7..7] 1=Enable pull-up resistors on Transmit p…
27017 …__IO uint32_t QMSPI_STATUS; /*!< (@ 0x40005410) QMSPI Status Register …
27020 …__IO uint32_t TRANSFER_COMPLETE: 1; /*!< [0..0] In Manual Mode (neither DMA nor Descript…
27030 …__IO uint32_t DMA_COMPLETE: 1; /*!< [1..1] This field has no meaning if DMA is not …
27040 …__IO uint32_t TRANSMIT_BUFFER_ERROR: 1; /*!< [2..2] 1=Overflow error occurred (attempt to wr…
27043 …__IO uint32_t RECEIVE_BUFFER_ERROR: 1; /*!< [3..3] 1=Underflow error occurred (attempt to r…
27046 …__IO uint32_t PROGRAMMING_ERROR: 1; /*!< [4..4] This bit if a programming error is detec…
27054 …__IO uint32_t TRANSMIT_BUFFER_REQUEST: 1; /*!< [10..10] This status is asserted if the Transmi…
27060 …__IO uint32_t TRANSMIT_BUFFER_STALL: 1; /*!< [11..11] 1=The SPI interface had been stalled d…
27068 …__IO uint32_t RECEIVE_BUFFER_REQUEST: 1; /*!< [14..14] This status is asserted if the Receive…
27074 …__IO uint32_t RECEIVE_BUFFER_STALL: 1; /*!< [15..15] 1=The SPI interface had been stalled d…
27088 …__IO uint32_t QMSPI_BUFFER_COUNT_STATUS; /*!< (@ 0x40005414) QMSPI Buffer Count Status Regi…
27091 …__IO uint32_t TRANSMIT_BUFFER_COUNT: 16; /*!< [0..15] This is a count of the number of bytes …
27093 …__IO uint32_t RECEIVE_BUFFER_COUNT: 16; /*!< [16..31] This is a count of the number of bytes…
27099 …__IO uint32_t QMSPI_INTERRUPT_ENABLE; /*!< (@ 0x40005418) QMSPI Interrupt Enable Registe…
27102 …__IO uint32_t TRANSFER_COMPLETE_ENABLE: 1; /*!< [0..0] 1=Enable an interrupt if TRANSFER_COMPLE…
27104 …__IO uint32_t DMA_COMPLETE_ENABLE: 1; /*!< [1..1] 1=Enable an interrupt if DMA_COMPLETE is…
27106 …__IO uint32_t TRANSMIT_BUFFER_ERROR_ENABLE: 1;/*!< [2..2] 1=Enable an interrupt if TRANSMIT_BUFF…
27108 …__IO uint32_t RECEIVE_BUFFER_ERROR_ENABLE: 1;/*!< [3..3] 1=Enable an interrupt if RECEIVE_BUFFER…
27110 …__IO uint32_t PROGRAMMING_ERROR_ENABLE: 1; /*!< [4..4] 1=Enable an interrupt if PROGRAMMING_ERR…
27117 …__IO uint32_t TRANSMIT_BUFFER_REQUEST_ENABLE: 1;/*!< [10..10] 1=Enable an interrupt if TRANSMIT_…
27125 …__IO uint32_t RECEIVE_BUFFER_REQUEST_ENABLE: 1;/*!< [14..14] 1=Enable an interrupt if RECEIVE_BU…
27132 …__IO uint32_t QMSPI_BUFFER_COUNT_TRIGGER; /*!< (@ 0x4000541C) QMSPI Buffer Count Trigger Reg…
27135 …__IO uint32_t TRANSMIT_BUFFER_TRIGGER: 16; /*!< [0..15] An interrupt is triggered if the TRANSM…
27138 …__IO uint32_t RECEIVE_BUFFER_TRIGGER: 16; /*!< [16..31] An interrupt is triggered if the RECEI…
27145 …__IO uint32_t QMSPI_TRAMSMIT_BUFFER; /*!< (@ 0x40005420) QMSPI Transmit Buffer Register…
27162 …__IO uint32_t QMSPI_RECEIVE_BUFFER; /*!< (@ 0x40005424) QMSPI Receive Buffer Register …
27180 …__IO uint32_t QMSPI_DESCRIPTION_BUFFER_0; /*!< (@ 0x40005430) QMSPI Description Buffer 0 Reg…
27183 …__IO uint32_t INTERFACE_MODE: 2; /*!< [0..1] This field sets the transmission mode. I…
27188 …__IO uint32_t TX_TRANSFER_ENABLE: 2; /*!< [2..3] This field bit selects the transmit func…
27198 …__IO uint32_t TX_DMA_ENABLE: 2; /*!< [4..5] This bit enables DMA support for Transmi…
27207 …__IO uint32_t RX_TRANSFER_ENABLE: 1; /*!< [6..6] This bit enables the receive function of…
27227 __IO uint32_t TRANSFER_LENGTH_BITS: 1; /*!< [10..10] 1=TRANSFER_LENGTH defined in bits
27238 …__IO uint32_t TRANSFER_LENGTH: 16; /*!< [16..31] The length of the SPI transfer. The co…
27245 …__IO uint32_t QMSPI_DESCRIPTION_BUFFER_1; /*!< (@ 0x40005434) QMSPI Description Buffer 1 Reg…
27248 …__IO uint32_t INTERFACE_MODE: 2; /*!< [0..1] This field sets the transmission mode. I…
27253 …__IO uint32_t TX_TRANSFER_ENABLE: 2; /*!< [2..3] This field bit selects the transmit func…
27263 …__IO uint32_t TX_DMA_ENABLE: 2; /*!< [4..5] This bit enables DMA support for Transmi…
27272 …__IO uint32_t RX_TRANSFER_ENABLE: 1; /*!< [6..6] This bit enables the receive function of…
27292 __IO uint32_t TRANSFER_LENGTH_BITS: 1; /*!< [10..10] 1=TRANSFER_LENGTH defined in bits
27303 …__IO uint32_t TRANSFER_LENGTH: 16; /*!< [16..31] The length of the SPI transfer. The co…
27310 …__IO uint32_t QMSPI_DESCRIPTION_BUFFER_2; /*!< (@ 0x40005438) QMSPI Description Buffer 2 Reg…
27313 …__IO uint32_t INTERFACE_MODE: 2; /*!< [0..1] This field sets the transmission mode. I…
27318 …__IO uint32_t TX_TRANSFER_ENABLE: 2; /*!< [2..3] This field bit selects the transmit func…
27328 …__IO uint32_t TX_DMA_ENABLE: 2; /*!< [4..5] This bit enables DMA support for Transmi…
27337 …__IO uint32_t RX_TRANSFER_ENABLE: 1; /*!< [6..6] This bit enables the receive function of…
27357 __IO uint32_t TRANSFER_LENGTH_BITS: 1; /*!< [10..10] 1=TRANSFER_LENGTH defined in bits
27368 …__IO uint32_t TRANSFER_LENGTH: 16; /*!< [16..31] The length of the SPI transfer. The co…
27375 …__IO uint32_t QMSPI_DESCRIPTION_BUFFER_3; /*!< (@ 0x4000543C) QMSPI Description Buffer 3 Reg…
27378 …__IO uint32_t INTERFACE_MODE: 2; /*!< [0..1] This field sets the transmission mode. I…
27383 …__IO uint32_t TX_TRANSFER_ENABLE: 2; /*!< [2..3] This field bit selects the transmit func…
27393 …__IO uint32_t TX_DMA_ENABLE: 2; /*!< [4..5] This bit enables DMA support for Transmi…
27402 …__IO uint32_t RX_TRANSFER_ENABLE: 1; /*!< [6..6] This bit enables the receive function of…
27422 __IO uint32_t TRANSFER_LENGTH_BITS: 1; /*!< [10..10] 1=TRANSFER_LENGTH defined in bits
27433 …__IO uint32_t TRANSFER_LENGTH: 16; /*!< [16..31] The length of the SPI transfer. The co…
27440 …__IO uint32_t QMSPI_DESCRIPTION_BUFFER_4; /*!< (@ 0x40005440) QMSPI Description Buffer 4 Reg…
27443 …__IO uint32_t INTERFACE_MODE: 2; /*!< [0..1] This field sets the transmission mode. I…
27448 …__IO uint32_t TX_TRANSFER_ENABLE: 2; /*!< [2..3] This field bit selects the transmit func…
27458 …__IO uint32_t TX_DMA_ENABLE: 2; /*!< [4..5] This bit enables DMA support for Transmi…
27467 …__IO uint32_t RX_TRANSFER_ENABLE: 1; /*!< [6..6] This bit enables the receive function of…
27487 __IO uint32_t TRANSFER_LENGTH_BITS: 1; /*!< [10..10] 1=TRANSFER_LENGTH defined in bits
27498 …__IO uint32_t TRANSFER_LENGTH: 16; /*!< [16..31] The length of the SPI transfer. The co…
27526 …__IO uint32_t CONTROL; /*!< (@ 0x40009004) PS2 Control Register …
27529 __IO uint32_t TR : 1; /*!< [0..0] PS/2 Transmit/Receive
27532 …__IO uint32_t EN : 1; /*!< [1..1] PS/2 Enable. 0=The PS/2 state machine is…
27534 …__IO uint32_t PARITY : 2; /*!< [2..3] 00b=Receiver expects Odd Parity (default…
27539 …__IO uint32_t STOP : 2; /*!< [4..5] 00b=Receiver expects an active high stop…
27548 …__IO uint32_t STATUS; /*!< (@ 0x40009008) PS2 Status Register …
27554 …__IO uint32_t REC_TIMEOUT: 1; /*!< [1..1] Receive Timeout. The REC_TIMEOUT bit is …
27557 …__IO uint32_t PE : 1; /*!< [2..2] Parity Error …
27558 …__IO uint32_t FE : 1; /*!< [3..3] Framing Error …
27559 …__IO uint32_t XMIT_IDLE : 1; /*!< [4..4] Transmitter Idle. 0=The channel is activ…
27562 …__IO uint32_t XMIT_TIME_OUT: 1; /*!< [5..5] Transmitter Time-out. When the XMIT_TIME…
27566 __IO uint32_t RX_BUSY : 1; /*!< [6..6] Receive Channel Busy.
27569 __IO uint32_t XMIT_START_TIMEOUT: 1; /*!< [7..7] Transmit Start Timeout.
27593 …__IO uint32_t STATUS; /*!< (@ 0x4000CD00) BC-Link Status …
27599 …__IO uint32_t BUSY_CLR_INT_EN: 1; /*!< [4..4] This bit is an enable for generating an …
27605 …__IO uint32_t ERR_INT_EN : 1; /*!< [5..5] This bit is an enable for generating an …
27609 …__IO uint32_t ERROR : 1; /*!< [6..6] This bit indicates that a BC Bus Error h…
27611 …__IO uint32_t RESET : 1; /*!< [7..7] When this bit is '1'the BC_Link Master I…
27619 …__IO uint32_t ADDRESS; /*!< (@ 0x4000CD04) BC-Link Address Register [7:…
27621 …__IO uint32_t DATA_REG; /*!< (@ 0x4000CD08) BC-Link Data Register [7:0] …
27623 …__IO uint32_t CLOCK_SELECT; /*!< (@ 0x4000CD0C) BC-Link Clock Select Registe…
27643 …__IO uint8_t DEBUG_DATA; /*!< (@ 0x40008C00) Debug data to be shifted out…
27650 …__IO uint8_t DEBUG_CONTROL; /*!< (@ 0x40008C04) Debug Control Register …
27653 …__IO uint8_t EN : 1; /*!< [0..0] Enable. 1=Clock enabled, 0=Clock is disa…
27655 …__IO uint8_t EDGE_SEL : 1; /*!< [1..1] 1= Data is shifted out on the falling ed…
27658 …__IO uint8_t DIVSEL : 2; /*!< [2..3] Clock Divider Select. …
27659 …__IO uint8_t IP_DELAY : 3; /*!< [4..6] Inter-packet Delay. The delay is in term…
27689 …__IO uint32_t EC_DATA; /*!< (@ 0x400F8100) EC Data Register. …
27698 …__IO uint32_t CONFIGURATION; /*!< (@ 0x400F8104) Configuration Register. …
27710 …__IO uint32_t TIMEBASE_SELECT: 2; /*!< [3..4] These bits determine the clock for the 2…
27712 …__IO uint32_t TIMER_ENABLE: 1; /*!< [5..5] When the TIMER_ENABLE bit is 1, the 24-b…
27715 …__IO uint32_t FIFO_THRESHOLD: 2; /*!< [6..7] This field determines the threshold for …
27734 …__IO uint32_t COUNT; /*!< (@ 0x400F810C) Count Register …
27738 …__IO uint32_t COUNT : 24; /*!< [8..31] Writes load data into the 24-bit Timer.…
27745 …__IO uint32_t ACTIVATE; /*!< (@ 0x400F8330) Activate Register …
27748 …__IO uint32_t ACTIVATE : 1; /*!< [0..0] When this bit is asserted 1, the block i…
27773 …__IO uint32_t VCI_REG; /*!< (@ 0x4000AE00) VCI Register …
27790 …__IO uint32_t VCI_FW_CNTRL: 1; /*!< [10..10] This bit can allow EC firmware to cont…
27798 …__IO uint32_t FW_EXT : 1; /*!< [11..11] This bit controls selecting between th…
27807 …__IO uint32_t FILTERS_BYPASS: 1; /*!< [12..12] The Filters Bypass bit is used to enab…
27821 …__IO uint32_t LATCH_ENABLE; /*!< (@ 0x4000AE04) Latch Enable Register …
27824 …__IO uint32_t LE : 7; /*!< [0..6] Latching Enables. Latching occurs after …
27834 …__IO uint32_t WEEK_ALRM_LE: 1; /*!< [16..16] Latch enable for the Week Alarm Power-…
27839 …__IO uint32_t RTC_ALRM_LE: 1; /*!< [17..17] Latch enable for the RTC Power-Up sign…
27848 …__IO uint32_t LATCH_RESETS; /*!< (@ 0x4000AE08) Latch Resets Register …
27875 …__IO uint32_t VCI_INPUT_ENABLE; /*!< (@ 0x4000AE0C) VCI Input Enable Register …
27878 …__IO uint32_t IE : 7; /*!< [0..6] Input Enables for VCI_IN# signals. After…
27893 …__IO uint32_t HOLDOFF_COUNT; /*!< (@ 0x4000AE10) Holdoff Count Register …
27896 …__IO uint32_t HOLDOFF_TIME: 8; /*!< [0..7] These bits determine the period of time …
27905 …__IO uint32_t VCI_POLARITY; /*!< (@ 0x4000AE14) VCI Polarity Register …
27908 …__IO uint32_t VCI_IN_POL : 7; /*!< [0..6] These bits determine the polarity of the…
27916 …__IO uint32_t VCI_POSEDGE_DETECT; /*!< (@ 0x4000AE18) VCI Posedge Detect Register …
27919 …__IO uint32_t VCI_IN_POS : 7; /*!< [0..6] These bits record a low to high transiti…
27927 …__IO uint32_t VCI_NEGEDGE_DETECT; /*!< (@ 0x4000AE1C) VCI Negedge Detect Register …
27930 …__IO uint32_t VCI_IN_NEG : 7; /*!< [0..6] These bits record a high to low transiti…
27938 …__IO uint32_t VCI_BUFFER_ENABLE; /*!< (@ 0x4000AE20) VCI Buffer Enable Register …
27941 …__IO uint32_t VCI_BUFFER_EN: 7; /*!< [0..6] Input Buffer enable. After changing the …
27969 …__IO uint32_t VBAT_RAM_DW_[32]; /*!< (@ 0x4000A800) 32-bits of VBAT powered RAM.…
27987 …__IO uint8_t PFR_STS; /*!< (@ 0x4000A400) The Power-Fail and Reset Statu…
27993 …__IO uint8_t SOFT : 1; /*!< [2..2] This bit is set to '1b' if a was trigger…
27997 …__IO uint8_t TEST : 1; /*!< [3..3] Test …
27998 …__IO uint8_t RESETI : 1; /*!< [4..4] This bit is set to '1b' if a RESET_SYS w…
28002 …__IO uint8_t WDT_EVT : 1; /*!< [5..5] This bit is set to '1b' if a RESET_SYS w…
28006 …__IO uint8_t SYSRESETREQ: 1; /*!< [6..6] This bit is set to '1b' if a RESET_SYS w…
28010 …__IO uint8_t VBAT_RST : 1; /*!< [7..7] The VBAT RST bit is set to '1' by hardwa…
28019 …__IO uint32_t CLOCK_EN; /*!< (@ 0x4000A408) CLOCK ENABLE …
28022 …__IO uint32_t C32K_SUPPRESS: 1; /*!< [0..0] 1=32KHz clock domain is off while VTR is…
28028 …__IO uint32_t EXT_32K : 1; /*!< [1..1] This bit selects the source for the 32KH…
28036 …__IO uint32_t C32KHZ_SOURCE: 1; /*!< [2..2] This field determines the source for the…
28046 …__IO uint32_t XOSEL : 1; /*!< [3..3] This bit selects between a single-ended …
28058 …__IO uint32_t MONOTONIC_COUNTER; /*!< (@ 0x4000A420) MONOTONIC COUNTER …
28067 …__IO uint32_t COUNTER_HIWORD; /*!< (@ 0x4000A424) COUNTER HIWORD …
28070 …__IO uint32_t COUNTER_HIWORD: 32; /*!< [0..31] Thirty-two bit read/write register. If …
28079 …__IO uint32_t VWIRE_BACKUP; /*!< (@ 0x4000A428) VWIRE_BACKUP …
28082 …__IO uint32_t M2S_2H_BACKUP: 4; /*!< [0..3] The Boot ROM firmware will copy this fie…
28090 …__IO uint32_t M2S_42H_BACKUP: 4; /*!< [4..7] The Boot ROM firmware will copy this fie…
28114 …__IO uint32_t AHB_ERROR_ADDRESS; /*!< (@ 0x4000FC04) AHB Error Address [0:0] AHB_…
28123 …__IO uint8_t AHB_ERROR_CONTROL; /*!< (@ 0x4000FC14) AHB Error Control [0:0] AHB_…
28127 …__IO uint32_t INTERRUPT_CONTROL; /*!< (@ 0x4000FC18) Interrupt Control [0:0] NVIC…
28133 …__IO uint32_t ETM_TRACE_ENABLE; /*!< (@ 0x4000FC1C) ETM TRACE Enable [0:0] TRACE…
28139 …__IO uint32_t DEBUG_Enable; /*!< (@ 0x4000FC20) Debug Enable Register …
28142 …__IO uint32_t DEBUG_EN : 1; /*!< [0..0] DEBUG_EN (JTAG_EN) This bit enables the …
28149 …__IO uint32_t DEBUG_PIN_CFG: 2; /*!< [1..2] This field determines which pins are aff…
28160 …__IO uint32_t DEBUG_PU_EN: 1; /*!< [3..3] If this bit is set to '1b' internal pull…
28171 …__IO uint32_t OTP_LOCK; /*!< (@ 0x4000FC24) OTP Lock …
28174 …__IO uint32_t TEST : 1; /*!< [0..0] Test …
28175 …__IO uint32_t MCHIP_LOCK : 1; /*!< [1..1] This bit controls access to Microchip re…
28183 …__IO uint32_t PRIVATE_KEY_LOCK: 1; /*!< [2..2] This bit controls access to Private Key …
28190 …__IO uint32_t USER_OTP_LOCK: 1; /*!< [3..3] This bit controls access to the User reg…
28197 …__IO uint32_t PUBLIC_KEY_LOCK: 1; /*!< [4..4] This bit controls access to the Public K…
28206 …__IO uint32_t WDT_EVENT_COUNT; /*!< (@ 0x4000FC28) WDT Event Count [3:0] WDT_CO…
28213 …__IO uint32_t AES_HASH_BYTE_SWAP_CONTROL; /*!< (@ 0x4000FC2C) AES HASH Byte Swap Control Reg…
28218 …__IO uint32_t OUTPUT_BYTE_SWAP_ENABLE: 1; /*!< [1..1] Used to enable byte swap on a DWORD duri…
28220 …__IO uint32_t INPUT_BLOCK_SWAP_ENABLE: 3; /*!< [2..4] Used to enable word swap on a DWORD duri…
28230 …__IO uint32_t OUTPUT_BLOCK_SWAP_ENABLE: 3; /*!< [5..7] Used to enable word swap on a DWORD duri…
28245 …__IO uint32_t PECI_DISABLE; /*!< (@ 0x4000FC40) PECI Disable …
28255 …__IO uint32_t CRYPTO_SOFT_RESET; /*!< (@ 0x4000FC5C) System Shutdown Reset …
28269 …__IO uint32_t GPIO_BANK_POWER; /*!< (@ 0x4000FC64) GPIO Bank Power Register …
28272 …__IO uint32_t VTR_LEVEL1 : 1; /*!< [0..0] Voltage value on VTR1. This bit is set b…
28279 …__IO uint32_t VTR_LEVEL2 : 1; /*!< [1..1] Voltage value on VTR2. This bit is set b…
28286 …__IO uint32_t VTR_LEVEL3 : 1; /*!< [2..2] Voltage value on VTR3. This bit is set b…
28294 …__IO uint32_t GPIO_BANK_POWER_LOCK: 1; /*!< [7..7] GPIO Bank Power Lock. 0: VTR_LEVEL bits[…
28303 …__IO uint32_t JTAG_MASTER_CFG; /*!< (@ 0x4000FC70) JTAG Master Configuration Regi…
28306 …__IO uint32_t JTM_CLK : 3; /*!< [0..2] This field determines the JTAG Master cl…
28310 …__IO uint32_t MASTER_SLAVE: 1; /*!< [3..3] This bit controls the direction of the J…
28331 …__IO uint32_t JTAG_MASTER_TDO; /*!< (@ 0x4000FC78) JTAG Master TDO Register …
28334 …__IO uint32_t JTM_TDO : 32; /*!< [0..31] When the JTAG Master Command Register i…
28344 …__IO uint32_t JTAG_MASTER_TDI; /*!< (@ 0x4000FC7C) JTAG Master TDI Register …
28347 …__IO uint32_t JTM_TDI : 32; /*!< [0..31] When the JTAG Master Command Register i…
28357 …__IO uint32_t JTAG_MASTER_TMS; /*!< (@ 0x4000FC80) JTAG Master TMS Register …
28360 …__IO uint32_t JTM_TMS : 32; /*!< [0..31] When the JTAG Master Command Register i…
28370 …__IO uint32_t JTAG_MASTER_CMD; /*!< (@ 0x4000FC84) JTAG Master Command Register …
28373 …__IO uint32_t JTM_COUNT : 5; /*!< [0..4] If the JTAG Port is configured as a Mast…
28402 …__IO uint32_t CONTROL; /*!< (@ 0x40082000) eFUSE CONTROL Register …
28407 …__IO uint32_t RESET : 1; /*!< [1..1] Block reset: 1=Block is reset; 0=Normal …
28409 …__IO uint32_t EXT_PGM : 1; /*!< [2..2] External programming enable: 1=eFUSE pro…
28412 …__IO uint32_t FSOURCE_EN_PRGM: 1; /*!< [3..3] FSOURCE pin enable for programming: 1=FS…
28419 …__IO uint32_t FSOURCE_EN_READ: 1; /*!< [4..4] FSOURCE pin enable for reading: 1=FSOURC…
28429 …__IO uint16_t MANUAL_CONTROL; /*!< (@ 0x40082004) Manual Control Register …
28437 …__IO uint16_t IP_CS : 1; /*!< [1..1] eFUSE chip select (CS) pin: 1=eFUSE is e…
28439 …__IO uint16_t IP_PRGM_EN : 1; /*!< [2..2] eFUSE program enable. Can also be consid…
28441 …__IO uint16_t IP_PRCHG : 1; /*!< [3..3] eFUSE precharge: 1=outputs are being pre…
28443 …__IO uint16_t IP_SENSE_PULSE: 1; /*!< [4..4] eFUSE sense, outputs are valid on fallin…
28445 …__IO uint16_t IP_OE : 1; /*!< [5..5] eFUSE output enable. The IP might tri-st…
28453 …__IO uint16_t MANUAL_MODE_ADDRESS; /*!< (@ 0x40082006) MANUAL MODE ADDRESS REGISTER …
28456 …__IO uint16_t IP_ADDR_LO : 10; /*!< [0..9] Manual mode address, selecting the bit a…
28458 …__IO uint16_t IP_ADDR_HI : 2; /*!< [10..11] Manual mode address, selecting a 1K bi…
28465 …__IO uint32_t MANUAL_MODE_DATA; /*!< (@ 0x4008200C) MANUAL MODE DATA REGISTER …
28468 …__IO uint32_t IP_DATA : 16; /*!< [0..15] Manual mode data: This field connects t…
28472 …__IO uint32_t EFUSE_MEMORY_DW_[128]; /*!< (@ 0x40082010) 512 Bytes of EFUSE Memory (I…