1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_CAN_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_CAN_COMPONENT_FIXUP_H_ 9 10 /* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t ID:29; /*!< bit: 0..28 Identifier */ 15 uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ 16 uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ 17 uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ 18 } bit; /*!< Structure used for bit access */ 19 uint32_t reg; /*!< Type used for register access */ 20 } CAN_RXBE_0_Type; 21 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 22 23 /* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ 24 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 25 typedef union { 26 struct { 27 uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ 28 uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ 29 uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ 30 uint32_t FDF:1; /*!< bit: 21 FD Format */ 31 uint32_t :2; /*!< bit: 22..23 Reserved */ 32 uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ 33 uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ 34 } bit; /*!< Structure used for bit access */ 35 uint32_t reg; /*!< Type used for register access */ 36 } CAN_RXBE_1_Type; 37 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 38 39 /* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ 40 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 41 typedef union { 42 struct { 43 uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ 44 uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ 45 uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ 46 uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ 47 } bit; /*!< Structure used for bit access */ 48 uint32_t reg; /*!< Type used for register access */ 49 } CAN_RXBE_DATA_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 /* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ 53 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 54 typedef union { 55 struct { 56 uint32_t ID:29; /*!< bit: 0..28 Identifier */ 57 uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ 58 uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ 59 uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ 60 } bit; /*!< Structure used for bit access */ 61 uint32_t reg; /*!< Type used for register access */ 62 } CAN_RXF0E_0_Type; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 /* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ 66 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 67 typedef union { 68 struct { 69 uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ 70 uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ 71 uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ 72 uint32_t FDF:1; /*!< bit: 21 FD Format */ 73 uint32_t :2; /*!< bit: 22..23 Reserved */ 74 uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ 75 uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ 76 } bit; /*!< Structure used for bit access */ 77 uint32_t reg; /*!< Type used for register access */ 78 } CAN_RXF0E_1_Type; 79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 /* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ 82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 83 typedef union { 84 struct { 85 uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ 86 uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ 87 uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ 88 uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ 89 } bit; /*!< Structure used for bit access */ 90 uint32_t reg; /*!< Type used for register access */ 91 } CAN_RXF0E_DATA_Type; 92 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 /* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ 95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 96 typedef union { 97 struct { 98 uint32_t ID:29; /*!< bit: 0..28 Identifier */ 99 uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ 100 uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ 101 uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ 102 } bit; /*!< Structure used for bit access */ 103 uint32_t reg; /*!< Type used for register access */ 104 } CAN_RXF1E_0_Type; 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 106 107 /* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { 110 struct { 111 uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ 112 uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ 113 uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ 114 uint32_t FDF:1; /*!< bit: 21 FD Format */ 115 uint32_t :2; /*!< bit: 22..23 Reserved */ 116 uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ 117 uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ 118 } bit; /*!< Structure used for bit access */ 119 uint32_t reg; /*!< Type used for register access */ 120 } CAN_RXF1E_1_Type; 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 /* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ 124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 125 typedef union { 126 struct { 127 uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ 128 uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ 129 uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ 130 uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ 131 } bit; /*!< Structure used for bit access */ 132 uint32_t reg; /*!< Type used for register access */ 133 } CAN_RXF1E_DATA_Type; 134 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 135 136 /* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 138 typedef union { 139 struct { 140 uint32_t ID:29; /*!< bit: 0..28 Identifier */ 141 uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ 142 uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ 143 uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ 144 } bit; /*!< Structure used for bit access */ 145 uint32_t reg; /*!< Type used for register access */ 146 } CAN_TXBE_0_Type; 147 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 148 149 /* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 151 typedef union { 152 struct { 153 uint32_t :16; /*!< bit: 0..15 Reserved */ 154 uint32_t DLC:4; /*!< bit: 16..19 Identifier */ 155 uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ 156 uint32_t FDF:1; /*!< bit: 21 FD Format */ 157 uint32_t :1; /*!< bit: 22 Reserved */ 158 uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ 159 uint32_t MM:8; /*!< bit: 24..31 Message Marker */ 160 } bit; /*!< Structure used for bit access */ 161 uint32_t reg; /*!< Type used for register access */ 162 } CAN_TXBE_1_Type; 163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 164 165 /* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { 168 struct { 169 uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ 170 uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ 171 uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ 172 uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ 173 } bit; /*!< Structure used for bit access */ 174 uint32_t reg; /*!< Type used for register access */ 175 } CAN_TXBE_DATA_Type; 176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 /* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint32_t ID:29; /*!< bit: 0..28 Identifier */ 183 uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ 184 uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ 185 uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ 186 } bit; /*!< Structure used for bit access */ 187 uint32_t reg; /*!< Type used for register access */ 188 } CAN_TXEFE_0_Type; 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 /* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ 192 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 193 typedef union { 194 struct { 195 uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ 196 uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ 197 uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ 198 uint32_t FDF:1; /*!< bit: 21 FD Format */ 199 uint32_t ET:2; /*!< bit: 22..23 Event Type */ 200 uint32_t MM:8; /*!< bit: 24..31 Message Marker */ 201 } bit; /*!< Structure used for bit access */ 202 uint32_t reg; /*!< Type used for register access */ 203 } CAN_TXEFE_1_Type; 204 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 205 206 /* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 208 typedef union { 209 struct { 210 uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ 211 uint32_t :5; /*!< bit: 11..15 Reserved */ 212 uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ 213 uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ 214 uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ 215 } bit; /*!< Structure used for bit access */ 216 uint32_t reg; /*!< Type used for register access */ 217 } CAN_SIDFE_0_Type; 218 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 219 220 /* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ 221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 222 typedef union { 223 struct { 224 uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ 225 uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ 226 } bit; /*!< Structure used for bit access */ 227 uint32_t reg; /*!< Type used for register access */ 228 } CAN_XIDFE_0_Type; 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 230 231 /* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ 232 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 233 typedef union { 234 struct { 235 uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ 236 uint32_t :1; /*!< bit: 29 Reserved */ 237 uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ 238 } bit; /*!< Structure used for bit access */ 239 uint32_t reg; /*!< Type used for register access */ 240 } CAN_XIDFE_1_Type; 241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 242 243 /* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ 244 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 245 typedef union { 246 struct { 247 uint32_t :20; /*!< bit: 0..19 Reserved */ 248 uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ 249 uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ 250 uint32_t REL:4; /*!< bit: 28..31 Core Release */ 251 } bit; /*!< Structure used for bit access */ 252 uint32_t reg; /*!< Type used for register access */ 253 } CAN_CREL_Type; 254 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 255 256 /* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ 257 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 258 typedef union { 259 struct { 260 uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ 261 } bit; /*!< Structure used for bit access */ 262 uint32_t reg; /*!< Type used for register access */ 263 } CAN_ENDN_Type; 264 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 265 /* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ 266 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 267 typedef union { 268 struct { 269 uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ 270 uint32_t :30; /*!< bit: 2..31 Reserved */ 271 } bit; /*!< Structure used for bit access */ 272 uint32_t reg; /*!< Type used for register access */ 273 } CAN_MRCFG_Type; 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 275 276 /* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ 277 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 278 typedef union { 279 struct { 280 uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ 281 uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ 282 uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ 283 uint32_t :3; /*!< bit: 13..15 Reserved */ 284 uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ 285 uint32_t :2; /*!< bit: 21..22 Reserved */ 286 uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ 287 uint32_t :8; /*!< bit: 24..31 Reserved */ 288 } bit; /*!< Structure used for bit access */ 289 uint32_t reg; /*!< Type used for register access */ 290 } CAN_DBTP_Type; 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 292 /* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 294 typedef union { 295 struct { 296 uint32_t :4; /*!< bit: 0.. 3 Reserved */ 297 uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ 298 uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ 299 uint32_t RX:1; /*!< bit: 7 Receive Pin */ 300 uint32_t :24; /*!< bit: 8..31 Reserved */ 301 } bit; /*!< Structure used for bit access */ 302 uint32_t reg; /*!< Type used for register access */ 303 } CAN_TEST_Type; 304 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 305 306 /* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ 307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 308 typedef union { 309 struct { 310 uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ 311 uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ 312 uint32_t :16; /*!< bit: 16..31 Reserved */ 313 } bit; /*!< Structure used for bit access */ 314 uint32_t reg; /*!< Type used for register access */ 315 } CAN_RWD_Type; 316 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 317 318 /* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ 319 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 320 typedef union { 321 struct { 322 uint32_t INIT:1; /*!< bit: 0 Initialization */ 323 uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ 324 uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ 325 uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ 326 uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ 327 uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ 328 uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ 329 uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ 330 uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ 331 uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ 332 uint32_t :2; /*!< bit: 10..11 Reserved */ 333 uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ 334 uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ 335 uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ 336 uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ 337 uint32_t :16; /*!< bit: 16..31 Reserved */ 338 } bit; /*!< Structure used for bit access */ 339 uint32_t reg; /*!< Type used for register access */ 340 } CAN_CCCR_Type; 341 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 342 /* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 344 typedef union { 345 struct { 346 uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ 347 uint32_t :1; /*!< bit: 7 Reserved */ 348 uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ 349 uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ 350 uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ 351 } bit; /*!< Structure used for bit access */ 352 uint32_t reg; /*!< Type used for register access */ 353 } CAN_NBTP_Type; 354 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 355 356 /* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ 357 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 358 typedef union { 359 struct { 360 uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ 361 uint32_t :14; /*!< bit: 2..15 Reserved */ 362 uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ 363 uint32_t :12; /*!< bit: 20..31 Reserved */ 364 } bit; /*!< Structure used for bit access */ 365 uint32_t reg; /*!< Type used for register access */ 366 } CAN_TSCC_Type; 367 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 368 369 /* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ 370 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 371 typedef union { 372 struct { 373 uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ 374 uint32_t :16; /*!< bit: 16..31 Reserved */ 375 } bit; /*!< Structure used for bit access */ 376 uint32_t reg; /*!< Type used for register access */ 377 } CAN_TSCV_Type; 378 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 379 380 /* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ 381 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 382 typedef union { 383 struct { 384 uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ 385 uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ 386 uint32_t :13; /*!< bit: 3..15 Reserved */ 387 uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ 388 } bit; /*!< Structure used for bit access */ 389 uint32_t reg; /*!< Type used for register access */ 390 } CAN_TOCC_Type; 391 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 392 393 /* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ 394 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 395 typedef union { 396 struct { 397 uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ 398 uint32_t :16; /*!< bit: 16..31 Reserved */ 399 } bit; /*!< Structure used for bit access */ 400 uint32_t reg; /*!< Type used for register access */ 401 } CAN_TOCV_Type; 402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 403 /* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef union { 406 struct { 407 uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ 408 uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ 409 uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ 410 uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ 411 uint32_t :8; /*!< bit: 24..31 Reserved */ 412 } bit; /*!< Structure used for bit access */ 413 uint32_t reg; /*!< Type used for register access */ 414 } CAN_ECR_Type; 415 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 416 /* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ 417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 418 typedef union { 419 struct { 420 uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ 421 uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ 422 uint32_t EP:1; /*!< bit: 5 Error Passive */ 423 uint32_t EW:1; /*!< bit: 6 Warning Status */ 424 uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ 425 uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ 426 uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ 427 uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ 428 uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ 429 uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ 430 uint32_t :1; /*!< bit: 15 Reserved */ 431 uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ 432 uint32_t :9; /*!< bit: 23..31 Reserved */ 433 } bit; /*!< Structure used for bit access */ 434 uint32_t reg; /*!< Type used for register access */ 435 } CAN_PSR_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 /* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ 438 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 439 typedef union { 440 struct { 441 uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ 442 uint32_t :1; /*!< bit: 7 Reserved */ 443 uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ 444 uint32_t :17; /*!< bit: 15..31 Reserved */ 445 } bit; /*!< Structure used for bit access */ 446 uint32_t reg; /*!< Type used for register access */ 447 } CAN_TDCR_Type; 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 449 /* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 451 typedef union { 452 struct { 453 uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ 454 uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ 455 uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ 456 uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ 457 uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ 458 uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ 459 uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ 460 uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ 461 uint32_t HPM:1; /*!< bit: 8 High Priority Message */ 462 uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ 463 uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ 464 uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ 465 uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ 466 uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ 467 uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ 468 uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ 469 uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ 470 uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ 471 uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ 472 uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ 473 uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ 474 uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ 475 uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ 476 uint32_t EP:1; /*!< bit: 23 Error Passive */ 477 uint32_t EW:1; /*!< bit: 24 Warning Status */ 478 uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ 479 uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ 480 uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ 481 uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ 482 uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ 483 uint32_t :2; /*!< bit: 30..31 Reserved */ 484 } bit; /*!< Structure used for bit access */ 485 uint32_t reg; /*!< Type used for register access */ 486 } CAN_IR_Type; 487 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 488 489 /* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 491 typedef union { 492 struct { 493 uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ 494 uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ 495 uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ 496 uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ 497 uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ 498 uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ 499 uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ 500 uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ 501 uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ 502 uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ 503 uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ 504 uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ 505 uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ 506 uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ 507 uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ 508 uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ 509 uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ 510 uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ 511 uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ 512 uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ 513 uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ 514 uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ 515 uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ 516 uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ 517 uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ 518 uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ 519 uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ 520 uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ 521 uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ 522 uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ 523 uint32_t :2; /*!< bit: 30..31 Reserved */ 524 } bit; /*!< Structure used for bit access */ 525 uint32_t reg; /*!< Type used for register access */ 526 } CAN_IE_Type; 527 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 528 /* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ 529 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 530 typedef union { 531 struct { 532 uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ 533 uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ 534 uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ 535 uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ 536 uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ 537 uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ 538 uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ 539 uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ 540 uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ 541 uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ 542 uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ 543 uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ 544 uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ 545 uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ 546 uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ 547 uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ 548 uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ 549 uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ 550 uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ 551 uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ 552 uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ 553 uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ 554 uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ 555 uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ 556 uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ 557 uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ 558 uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ 559 uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ 560 uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ 561 uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ 562 uint32_t :2; /*!< bit: 30..31 Reserved */ 563 } bit; /*!< Structure used for bit access */ 564 uint32_t reg; /*!< Type used for register access */ 565 } CAN_ILS_Type; 566 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 567 568 /* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ 569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 570 typedef union { 571 struct { 572 uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ 573 uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ 574 uint32_t :30; /*!< bit: 2..31 Reserved */ 575 } bit; /*!< Structure used for bit access */ 576 uint32_t reg; /*!< Type used for register access */ 577 } CAN_ILE_Type; 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 579 580 /* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ 581 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 582 typedef union { 583 struct { 584 uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ 585 uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ 586 uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ 587 uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ 588 uint32_t :26; /*!< bit: 6..31 Reserved */ 589 } bit; /*!< Structure used for bit access */ 590 uint32_t reg; /*!< Type used for register access */ 591 } CAN_GFC_Type; 592 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 593 594 /* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ 595 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 596 typedef union { 597 struct { 598 uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ 599 uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ 600 uint32_t :8; /*!< bit: 24..31 Reserved */ 601 } bit; /*!< Structure used for bit access */ 602 uint32_t reg; /*!< Type used for register access */ 603 } CAN_SIDFC_Type; 604 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 605 606 /* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ 607 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 608 typedef union { 609 struct { 610 uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ 611 uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ 612 uint32_t :9; /*!< bit: 23..31 Reserved */ 613 } bit; /*!< Structure used for bit access */ 614 uint32_t reg; /*!< Type used for register access */ 615 } CAN_XIDFC_Type; 616 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 617 618 /* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ 619 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 620 typedef union { 621 struct { 622 uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ 623 uint32_t :3; /*!< bit: 29..31 Reserved */ 624 } bit; /*!< Structure used for bit access */ 625 uint32_t reg; /*!< Type used for register access */ 626 } CAN_XIDAM_Type; 627 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 628 629 /* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ 630 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 631 typedef union { 632 struct { 633 uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ 634 uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ 635 uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ 636 uint32_t FLST:1; /*!< bit: 15 Filter List */ 637 uint32_t :16; /*!< bit: 16..31 Reserved */ 638 } bit; /*!< Structure used for bit access */ 639 uint32_t reg; /*!< Type used for register access */ 640 } CAN_HPMS_Type; 641 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 642 643 /* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ 644 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 645 typedef union { 646 struct { 647 uint32_t ND0:1; /*!< bit: 0 New Data 0 */ 648 uint32_t ND1:1; /*!< bit: 1 New Data 1 */ 649 uint32_t ND2:1; /*!< bit: 2 New Data 2 */ 650 uint32_t ND3:1; /*!< bit: 3 New Data 3 */ 651 uint32_t ND4:1; /*!< bit: 4 New Data 4 */ 652 uint32_t ND5:1; /*!< bit: 5 New Data 5 */ 653 uint32_t ND6:1; /*!< bit: 6 New Data 6 */ 654 uint32_t ND7:1; /*!< bit: 7 New Data 7 */ 655 uint32_t ND8:1; /*!< bit: 8 New Data 8 */ 656 uint32_t ND9:1; /*!< bit: 9 New Data 9 */ 657 uint32_t ND10:1; /*!< bit: 10 New Data 10 */ 658 uint32_t ND11:1; /*!< bit: 11 New Data 11 */ 659 uint32_t ND12:1; /*!< bit: 12 New Data 12 */ 660 uint32_t ND13:1; /*!< bit: 13 New Data 13 */ 661 uint32_t ND14:1; /*!< bit: 14 New Data 14 */ 662 uint32_t ND15:1; /*!< bit: 15 New Data 15 */ 663 uint32_t ND16:1; /*!< bit: 16 New Data 16 */ 664 uint32_t ND17:1; /*!< bit: 17 New Data 17 */ 665 uint32_t ND18:1; /*!< bit: 18 New Data 18 */ 666 uint32_t ND19:1; /*!< bit: 19 New Data 19 */ 667 uint32_t ND20:1; /*!< bit: 20 New Data 20 */ 668 uint32_t ND21:1; /*!< bit: 21 New Data 21 */ 669 uint32_t ND22:1; /*!< bit: 22 New Data 22 */ 670 uint32_t ND23:1; /*!< bit: 23 New Data 23 */ 671 uint32_t ND24:1; /*!< bit: 24 New Data 24 */ 672 uint32_t ND25:1; /*!< bit: 25 New Data 25 */ 673 uint32_t ND26:1; /*!< bit: 26 New Data 26 */ 674 uint32_t ND27:1; /*!< bit: 27 New Data 27 */ 675 uint32_t ND28:1; /*!< bit: 28 New Data 28 */ 676 uint32_t ND29:1; /*!< bit: 29 New Data 29 */ 677 uint32_t ND30:1; /*!< bit: 30 New Data 30 */ 678 uint32_t ND31:1; /*!< bit: 31 New Data 31 */ 679 } bit; /*!< Structure used for bit access */ 680 uint32_t reg; /*!< Type used for register access */ 681 } CAN_NDAT1_Type; 682 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 683 684 /* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ 685 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 686 typedef union { 687 struct { 688 uint32_t ND32:1; /*!< bit: 0 New Data 32 */ 689 uint32_t ND33:1; /*!< bit: 1 New Data 33 */ 690 uint32_t ND34:1; /*!< bit: 2 New Data 34 */ 691 uint32_t ND35:1; /*!< bit: 3 New Data 35 */ 692 uint32_t ND36:1; /*!< bit: 4 New Data 36 */ 693 uint32_t ND37:1; /*!< bit: 5 New Data 37 */ 694 uint32_t ND38:1; /*!< bit: 6 New Data 38 */ 695 uint32_t ND39:1; /*!< bit: 7 New Data 39 */ 696 uint32_t ND40:1; /*!< bit: 8 New Data 40 */ 697 uint32_t ND41:1; /*!< bit: 9 New Data 41 */ 698 uint32_t ND42:1; /*!< bit: 10 New Data 42 */ 699 uint32_t ND43:1; /*!< bit: 11 New Data 43 */ 700 uint32_t ND44:1; /*!< bit: 12 New Data 44 */ 701 uint32_t ND45:1; /*!< bit: 13 New Data 45 */ 702 uint32_t ND46:1; /*!< bit: 14 New Data 46 */ 703 uint32_t ND47:1; /*!< bit: 15 New Data 47 */ 704 uint32_t ND48:1; /*!< bit: 16 New Data 48 */ 705 uint32_t ND49:1; /*!< bit: 17 New Data 49 */ 706 uint32_t ND50:1; /*!< bit: 18 New Data 50 */ 707 uint32_t ND51:1; /*!< bit: 19 New Data 51 */ 708 uint32_t ND52:1; /*!< bit: 20 New Data 52 */ 709 uint32_t ND53:1; /*!< bit: 21 New Data 53 */ 710 uint32_t ND54:1; /*!< bit: 22 New Data 54 */ 711 uint32_t ND55:1; /*!< bit: 23 New Data 55 */ 712 uint32_t ND56:1; /*!< bit: 24 New Data 56 */ 713 uint32_t ND57:1; /*!< bit: 25 New Data 57 */ 714 uint32_t ND58:1; /*!< bit: 26 New Data 58 */ 715 uint32_t ND59:1; /*!< bit: 27 New Data 59 */ 716 uint32_t ND60:1; /*!< bit: 28 New Data 60 */ 717 uint32_t ND61:1; /*!< bit: 29 New Data 61 */ 718 uint32_t ND62:1; /*!< bit: 30 New Data 62 */ 719 uint32_t ND63:1; /*!< bit: 31 New Data 63 */ 720 } bit; /*!< Structure used for bit access */ 721 uint32_t reg; /*!< Type used for register access */ 722 } CAN_NDAT2_Type; 723 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 724 725 /* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ 726 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 727 typedef union { 728 struct { 729 uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ 730 uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ 731 uint32_t :1; /*!< bit: 23 Reserved */ 732 uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ 733 uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ 734 } bit; /*!< Structure used for bit access */ 735 uint32_t reg; /*!< Type used for register access */ 736 } CAN_RXF0C_Type; 737 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 738 /* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ 739 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 740 typedef union { 741 struct { 742 uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ 743 uint32_t :1; /*!< bit: 7 Reserved */ 744 uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ 745 uint32_t :2; /*!< bit: 14..15 Reserved */ 746 uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ 747 uint32_t :2; /*!< bit: 22..23 Reserved */ 748 uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ 749 uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ 750 uint32_t :6; /*!< bit: 26..31 Reserved */ 751 } bit; /*!< Structure used for bit access */ 752 uint32_t reg; /*!< Type used for register access */ 753 } CAN_RXF0S_Type; 754 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 755 756 /* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ 757 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 758 typedef union { 759 struct { 760 uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ 761 uint32_t :26; /*!< bit: 6..31 Reserved */ 762 } bit; /*!< Structure used for bit access */ 763 uint32_t reg; /*!< Type used for register access */ 764 } CAN_RXF0A_Type; 765 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 766 767 /* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ 768 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 769 typedef union { 770 struct { 771 uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ 772 uint32_t :16; /*!< bit: 16..31 Reserved */ 773 } bit; /*!< Structure used for bit access */ 774 uint32_t reg; /*!< Type used for register access */ 775 } CAN_RXBC_Type; 776 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 777 778 /* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ 779 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 780 typedef union { 781 struct { 782 uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ 783 uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ 784 uint32_t :1; /*!< bit: 23 Reserved */ 785 uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ 786 uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ 787 } bit; /*!< Structure used for bit access */ 788 uint32_t reg; /*!< Type used for register access */ 789 } CAN_RXF1C_Type; 790 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 791 792 /* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ 793 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 794 typedef union { 795 struct { 796 uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ 797 uint32_t :1; /*!< bit: 7 Reserved */ 798 uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ 799 uint32_t :2; /*!< bit: 14..15 Reserved */ 800 uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ 801 uint32_t :2; /*!< bit: 22..23 Reserved */ 802 uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ 803 uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ 804 uint32_t :4; /*!< bit: 26..29 Reserved */ 805 uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ 806 } bit; /*!< Structure used for bit access */ 807 uint32_t reg; /*!< Type used for register access */ 808 } CAN_RXF1S_Type; 809 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 810 811 /* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ 812 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 813 typedef union { 814 struct { 815 uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ 816 uint32_t :26; /*!< bit: 6..31 Reserved */ 817 } bit; /*!< Structure used for bit access */ 818 uint32_t reg; /*!< Type used for register access */ 819 } CAN_RXF1A_Type; 820 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 821 /* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ 822 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 823 typedef union { 824 struct { 825 uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ 826 uint32_t :1; /*!< bit: 3 Reserved */ 827 uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ 828 uint32_t :1; /*!< bit: 7 Reserved */ 829 uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ 830 uint32_t :21; /*!< bit: 11..31 Reserved */ 831 } bit; /*!< Structure used for bit access */ 832 uint32_t reg; /*!< Type used for register access */ 833 } CAN_RXESC_Type; 834 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 835 836 /* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ 837 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 838 typedef union { 839 struct { 840 uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ 841 uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ 842 uint32_t :2; /*!< bit: 22..23 Reserved */ 843 uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ 844 uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ 845 uint32_t :1; /*!< bit: 31 Reserved */ 846 } bit; /*!< Structure used for bit access */ 847 uint32_t reg; /*!< Type used for register access */ 848 } CAN_TXBC_Type; 849 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 850 851 /* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ 852 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 853 typedef union { 854 struct { 855 uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ 856 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 857 uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ 858 uint32_t :3; /*!< bit: 13..15 Reserved */ 859 uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ 860 uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ 861 uint32_t :10; /*!< bit: 22..31 Reserved */ 862 } bit; /*!< Structure used for bit access */ 863 uint32_t reg; /*!< Type used for register access */ 864 } CAN_TXFQS_Type; 865 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 866 867 /* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ 868 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 869 typedef union { 870 struct { 871 uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ 872 uint32_t :29; /*!< bit: 3..31 Reserved */ 873 } bit; /*!< Structure used for bit access */ 874 uint32_t reg; /*!< Type used for register access */ 875 } CAN_TXESC_Type; 876 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 877 878 /* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ 879 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 880 typedef union { 881 struct { 882 uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ 883 uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ 884 uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ 885 uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ 886 uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ 887 uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ 888 uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ 889 uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ 890 uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ 891 uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ 892 uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ 893 uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ 894 uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ 895 uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ 896 uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ 897 uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ 898 uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ 899 uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ 900 uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ 901 uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ 902 uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ 903 uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ 904 uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ 905 uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ 906 uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ 907 uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ 908 uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ 909 uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ 910 uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ 911 uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ 912 uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ 913 uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ 914 } bit; /*!< Structure used for bit access */ 915 uint32_t reg; /*!< Type used for register access */ 916 } CAN_TXBRP_Type; 917 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 918 919 /* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ 920 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 921 typedef union { 922 struct { 923 uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ 924 uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ 925 uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ 926 uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ 927 uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ 928 uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ 929 uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ 930 uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ 931 uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ 932 uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ 933 uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ 934 uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ 935 uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ 936 uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ 937 uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ 938 uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ 939 uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ 940 uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ 941 uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ 942 uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ 943 uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ 944 uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ 945 uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ 946 uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ 947 uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ 948 uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ 949 uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ 950 uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ 951 uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ 952 uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ 953 uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ 954 uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ 955 } bit; /*!< Structure used for bit access */ 956 uint32_t reg; /*!< Type used for register access */ 957 } CAN_TXBAR_Type; 958 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 959 960 /* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ 961 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 962 typedef union { 963 struct { 964 uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ 965 uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ 966 uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ 967 uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ 968 uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ 969 uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ 970 uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ 971 uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ 972 uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ 973 uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ 974 uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ 975 uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ 976 uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ 977 uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ 978 uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ 979 uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ 980 uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ 981 uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ 982 uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ 983 uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ 984 uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ 985 uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ 986 uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ 987 uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ 988 uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ 989 uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ 990 uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ 991 uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ 992 uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ 993 uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ 994 uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ 995 uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ 996 } bit; /*!< Structure used for bit access */ 997 uint32_t reg; /*!< Type used for register access */ 998 } CAN_TXBCR_Type; 999 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1000 1001 /* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ 1002 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1003 typedef union { 1004 struct { 1005 uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ 1006 uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ 1007 uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ 1008 uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ 1009 uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ 1010 uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ 1011 uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ 1012 uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ 1013 uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ 1014 uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ 1015 uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ 1016 uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ 1017 uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ 1018 uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ 1019 uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ 1020 uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ 1021 uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ 1022 uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ 1023 uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ 1024 uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ 1025 uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ 1026 uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ 1027 uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ 1028 uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ 1029 uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ 1030 uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ 1031 uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ 1032 uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ 1033 uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ 1034 uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ 1035 uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ 1036 uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ 1037 } bit; /*!< Structure used for bit access */ 1038 uint32_t reg; /*!< Type used for register access */ 1039 } CAN_TXBTO_Type; 1040 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1041 1042 /* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ 1043 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1044 typedef union { 1045 struct { 1046 uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ 1047 uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ 1048 uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ 1049 uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ 1050 uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ 1051 uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ 1052 uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ 1053 uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ 1054 uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ 1055 uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ 1056 uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ 1057 uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ 1058 uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ 1059 uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ 1060 uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ 1061 uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ 1062 uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ 1063 uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ 1064 uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ 1065 uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ 1066 uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ 1067 uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ 1068 uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ 1069 uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ 1070 uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ 1071 uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ 1072 uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ 1073 uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ 1074 uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ 1075 uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ 1076 uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ 1077 uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ 1078 } bit; /*!< Structure used for bit access */ 1079 uint32_t reg; /*!< Type used for register access */ 1080 } CAN_TXBCF_Type; 1081 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1082 1083 /* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ 1084 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1085 typedef union { 1086 struct { 1087 uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ 1088 uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ 1089 uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ 1090 uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ 1091 uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ 1092 uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ 1093 uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ 1094 uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ 1095 uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ 1096 uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ 1097 uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ 1098 uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ 1099 uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ 1100 uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ 1101 uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ 1102 uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ 1103 uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ 1104 uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ 1105 uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ 1106 uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ 1107 uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ 1108 uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ 1109 uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ 1110 uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ 1111 uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ 1112 uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ 1113 uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ 1114 uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ 1115 uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ 1116 uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ 1117 uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ 1118 uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ 1119 } bit; /*!< Structure used for bit access */ 1120 uint32_t reg; /*!< Type used for register access */ 1121 } CAN_TXBTIE_Type; 1122 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1123 1124 /* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ 1125 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1126 typedef union { 1127 struct { 1128 uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ 1129 uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ 1130 uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ 1131 uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ 1132 uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ 1133 uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ 1134 uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ 1135 uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ 1136 uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ 1137 uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ 1138 uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ 1139 uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ 1140 uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ 1141 uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ 1142 uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ 1143 uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ 1144 uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ 1145 uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ 1146 uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ 1147 uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ 1148 uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ 1149 uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ 1150 uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ 1151 uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ 1152 uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ 1153 uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ 1154 uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ 1155 uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ 1156 uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ 1157 uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ 1158 uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ 1159 uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ 1160 } bit; /*!< Structure used for bit access */ 1161 uint32_t reg; /*!< Type used for register access */ 1162 } CAN_TXBCIE_Type; 1163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1164 1165 /* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ 1166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1167 typedef union { 1168 struct { 1169 uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ 1170 uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ 1171 uint32_t :2; /*!< bit: 22..23 Reserved */ 1172 uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ 1173 uint32_t :2; /*!< bit: 30..31 Reserved */ 1174 } bit; /*!< Structure used for bit access */ 1175 uint32_t reg; /*!< Type used for register access */ 1176 } CAN_TXEFC_Type; 1177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1178 1179 /* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ 1180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1181 typedef union { 1182 struct { 1183 uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ 1184 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 1185 uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ 1186 uint32_t :3; /*!< bit: 13..15 Reserved */ 1187 uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ 1188 uint32_t :3; /*!< bit: 21..23 Reserved */ 1189 uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ 1190 uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ 1191 uint32_t :6; /*!< bit: 26..31 Reserved */ 1192 } bit; /*!< Structure used for bit access */ 1193 uint32_t reg; /*!< Type used for register access */ 1194 } CAN_TXEFS_Type; 1195 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1196 1197 /* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ 1198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1199 typedef union { 1200 struct { 1201 uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ 1202 uint32_t :27; /*!< bit: 5..31 Reserved */ 1203 } bit; /*!< Structure used for bit access */ 1204 uint32_t reg; /*!< Type used for register access */ 1205 } CAN_TXEFA_Type; 1206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1207 1208 /** \brief CAN Mram_rxbe hardware registers */ 1209 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1210 typedef struct { 1211 __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ 1212 __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ 1213 __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ 1214 } CanMramRxbe 1215 #ifdef __GNUC__ 1216 __attribute__ ((aligned (4))) 1217 #endif 1218 ; 1219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1220 1221 /** \brief CAN Mram_rxf0e hardware registers */ 1222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1223 typedef struct { 1224 __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ 1225 __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ 1226 __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ 1227 } CanMramRxf0e 1228 #ifdef __GNUC__ 1229 __attribute__ ((aligned (4))) 1230 #endif 1231 ; 1232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1233 1234 /** \brief CAN Mram_rxf1e hardware registers */ 1235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1236 typedef struct { 1237 __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ 1238 __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ 1239 __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ 1240 } CanMramRxf1e 1241 #ifdef __GNUC__ 1242 __attribute__ ((aligned (4))) 1243 #endif 1244 ; 1245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1246 1247 /** \brief CAN Mram_sidfe hardware registers */ 1248 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1249 typedef struct { 1250 __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ 1251 } CanMramSidfe 1252 #ifdef __GNUC__ 1253 __attribute__ ((aligned (4))) 1254 #endif 1255 ; 1256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1257 1258 /** \brief CAN Mram_txbe hardware registers */ 1259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1260 typedef struct { 1261 __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ 1262 __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ 1263 __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ 1264 } CanMramTxbe 1265 #ifdef __GNUC__ 1266 __attribute__ ((aligned (4))) 1267 #endif 1268 ; 1269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1270 1271 /** \brief CAN Mram_txefe hardware registers */ 1272 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1273 typedef struct { 1274 __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ 1275 __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ 1276 } CanMramTxefe 1277 #ifdef __GNUC__ 1278 __attribute__ ((aligned (4))) 1279 #endif 1280 ; 1281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1282 1283 /** \brief CAN Mram_xifde hardware registers */ 1284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1285 typedef struct { 1286 __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ 1287 __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ 1288 } CanMramXifde 1289 #ifdef __GNUC__ 1290 __attribute__ ((aligned (4))) 1291 #endif 1292 ; 1293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1294 1295 /** \brief CAN APB hardware registers */ 1296 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1297 typedef struct { 1298 __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ 1299 __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ 1300 __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ 1301 __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ 1302 __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ 1303 __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ 1304 __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ 1305 __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ 1306 __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ 1307 __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ 1308 __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ 1309 __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ 1310 RoReg8 Reserved1[0x10]; 1311 __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ 1312 __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ 1313 __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ 1314 RoReg8 Reserved2[0x4]; 1315 __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ 1316 __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ 1317 __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ 1318 __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ 1319 RoReg8 Reserved3[0x20]; 1320 __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ 1321 __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ 1322 __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ 1323 RoReg8 Reserved4[0x4]; 1324 __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ 1325 __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ 1326 __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ 1327 __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ 1328 __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ 1329 __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ 1330 __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ 1331 __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ 1332 __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ 1333 __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ 1334 __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ 1335 __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ 1336 __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ 1337 __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ 1338 __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ 1339 __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ 1340 __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ 1341 __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ 1342 __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ 1343 __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ 1344 __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ 1345 __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ 1346 RoReg8 Reserved5[0x8]; 1347 __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ 1348 __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ 1349 __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ 1350 } Can; 1351 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1352 1353 #define SECTION_CAN_MRAM_RXBE 1354 #define SECTION_CAN_MRAM_RXF0E 1355 #define SECTION_CAN_MRAM_RXF1E 1356 #define SECTION_CAN_MRAM_SIDFE 1357 #define SECTION_CAN_MRAM_TXBE 1358 #define SECTION_CAN_MRAM_TXEFE 1359 #define SECTION_CAN_MRAM_XIFDE 1360 1361 #endif /* _MICROCHIP_PIC32CXSG_CAN_COMPONENT_FIXUP_H_ */ 1362
