1 /*******************************************************************************
2  * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * MPFS HAL Embedded Software
7  *
8  */
9 
10 /*******************************************************************************
11  * @file mss_sgmii.h
12  * @author Microchip-FPGA Embedded Systems Solutions
13  * @brief SGMII defines
14  *
15  */
16 
17 #ifndef SRC_PLATFORM_MPFS_HAL_NWC_MSS_SGMII_H_
18 #define SRC_PLATFORM_MPFS_HAL_NWC_MSS_SGMII_H_
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 
25 #define REG_RX0_EN_OFFSET   (1U<<5U)
26 #define REG_RX1_EN_OFFSET   (1U<<7U)
27 #define TX_RX_CH_EN_MASK    0xFU
28 #define TX_RX_CH_EN_OFFSET  0x4U
29 #define REG_CDR_MOVE_STEP   (1U<<22U)   /* delay taps 1 => 3 taps moved, 0 => 2 taps move. */
30                                         /* 2 taps best for small PPM values, best results observed. */
31 
32 #define SHIFT_TO_CH0_N_EYE_VALUE    26U /* 26-28 */
33 #define SHIFT_TO_CH1_N_EYE_VALUE    29U /* 29-31 */
34 #define N_EYE_MASK                  0x03FFFFFFUL
35 
36 #define SHIFT_TO_REG_RX0_EYEWIDTH   21U
37 #define REG_RX0_EYEWIDTH_P_MASK     (~(0x7U<<SHIFT_TO_REG_RX0_EYEWIDTH))
38 #define SHIFT_TO_REG_RX1_EYEWIDTH   21U
39 #define REG_RX1_EYEWIDTH_P_MASK     (~(0x7U<<SHIFT_TO_REG_RX1_EYEWIDTH))
40 
41 #define REG_RX0_EN_FLAG_N   (1U<<31U)
42 #define REG_RX1_EN_FLAG_N   (1U<<31U)
43 
44 #if !defined (LIBERO_SETTING_MIN_DLL_90_CODE_VALUE_INDICATING_TT_PART_REVB)
45 #define MIN_DLL_90_CODE_VALUE_INDICATING_TT_PART_REVB  13
46 #endif
47 
48 #define ARO_REF_PCODE_MASK              0x3FUL
49 #if !defined (ARO_REF_PCODE_REVC_THRESHOLD)
50 #define ARO_REF_PCODE_REVC_THRESHOLD    0x40U
51 #endif
52 
53 /*
54  * For Rev B
55  * early (P) = 5/ Late (N) = 6
56  *
57  * e.g.
58  *      Channel control0: 0xB7B07770
59  *      Channel control1: 0xB7B07770
60  *      Spare control:    0xDB002680
61  *
62  *  early (P) = 6/ Late (N) = 7
63  *
64  *  e.g.
65  *      Channel control0: 0XB7D07770
66  *      Channel control1: 0XB7D07770
67  *      Spare control:    0XFF002680
68  *
69  *  Note: N eye width value set in spare control register
70  *              bits 31:29 for CH1,
71  *              bits 28:26  for CH0
72  *
73  *  For Rev C
74  *    early (P) = 7/ Late (N) = 6
75  */
76 
77 #if !defined (EARLY_EYE_WIDTH_PART_NOT_DETERMINED)
78 #define EARLY_EYE_WIDTH_PART_PART_NOT_DETERMINED  6U
79 #endif
80 #if !defined (START_EARLY_EYE_WIDTH_PART_REVC_OR_LATER)
81 #define EARLY_EYE_WIDTH_PART_REVC_OR_LATER  6U
82 #endif
83 #if !defined (START_EARLY_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST)
84 #define EARLY_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST  7U
85 #endif
86 #if !defined (EARLY_EYE_WIDTH_SS_PART_REVB)
87 #define EARLY_EYE_WIDTH_SS_PART_REVB        5U
88 #endif
89 #if !defined (EARLY_TT_PART_REVB)
90 #define EARLY_TT_PART_REVB                  6U
91 #endif
92 
93 
94 #if !defined (LATE_EYE_WIDTH_PART_NOT_DETERMINED)
95 #define LATE_EYE_WIDTH_PART_NOT_DETERMINED  7U
96 #endif
97 #if !defined (LATE_EYE_WIDTH_PART_REVC_OR_LATER)
98 #define LATE_EYE_WIDTH_PART_REVC_OR_LATER  7U
99 #endif
100 #if !defined (LATE_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST)
101 #define LATE_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST  6U
102 #endif
103 #if !defined (LATE_EYE_WIDTH_SS_PART_REVB)
104 #define LATE_EYE_WIDTH_SS_PART_REVB        6U
105 #endif
106 #if !defined (LATE_TT_PART_REVB)
107 #define LATE_TT_PART_REVB                  7U
108 #endif
109 
110 
111 typedef enum PART_TYPE_
112 {
113     PART_NOT_DETERMINED             = 0x00,       /*!< 0 default setting */
114     PART_REVC_OR_LATER              = 0x01,       /*!< 1 rev c or later  */
115     SS_PART_REVB                    = 0x02,       /*!< 2 SS part rev. B  */
116     TT_PART_REVB                    = 0x03,       /*!< 3 TT part rev. B  */
117     PART_TYPE_ARRAY_SIZE            = 0x04,       /*!< 4 array size  */
118 }   PART_TYPE;
119 
120 /**
121  * \brief bank control sgmii SCB regs
122  */
123 typedef struct IOSCB_BANK_CNTL_SGMII_ {
124                                     /* bit0 - This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit */
125                                     /* bit1 - This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit */
126     __IO uint32_t soft_reset;       /* bit8 - This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.       */
127 
128     __IO uint32_t dpc_bits;         /* DPC Bits Register            */
129     __IO uint32_t bank_status;      /* Bank Complete Registers      */
130 } IOSCB_BANK_CNTL_SGMII_STRUCT;
131 
132 
133 #define IOSCB_BANK_CNTL_SGMII_BASE  0x3E400000UL
134 #define IOSCB_BANK_CNTL_SGMII  ((volatile IOSCB_BANK_CNTL_SGMII_STRUCT *) IOSCB_BANK_CNTL_SGMII_BASE)
135 
136 
137 /**
138  * \brief dll sgmii SCB regs
139  */
140 typedef struct IOSCB_DLL_SGMII_ {
141                                     /* bit0 - This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit */
142                                     /* bit1 - This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit */
143     __IO uint32_t soft_reset;       /* bit8 - This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.       */
144 
145     __IO uint32_t dll_ctrl0;         /* DPC Bits Register            */
146     __IO uint32_t dll_ctrl1;         /* DPC Bits Register            */
147     __IO uint32_t dll_stat0;         /* DLL control register 0       */
148     __IO uint32_t dll_stat1;         /* DLL control register 1       */
149     __IO uint32_t dll_stat2;         /* DLL control register 2       */
150 } IOSCB_DLL_SGMII_STRUCT;
151 
152 
153 #define IOSCB_DLL_SGMII_BASE  0x3E100000UL
154 #define IOSCB_DLL_SGMII  ((volatile IOSCB_DLL_SGMII_STRUCT *) IOSCB_DLL_SGMII_BASE)
155 
156 
157 /**
158  * \brief gmiiphy_lanexx
159  */
160 typedef struct SGMIIPHY_LANE01_ {
161                                      /* bit0 - This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit */
162                                      /* bit1 - This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit */
163     __IO uint32_t soft_reset;        /* bit8 - This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0.       */
164 
165     __IO uint32_t BNK_CLK_SEL;       /*             */
166     __IO uint32_t dll_ctrl1;         /*             */
167     __IO uint32_t dll_stat0;         /*             */
168     __IO uint32_t dll_stat1;         /*             */
169     __IO uint32_t dll_stat2;         /*             */
170 } IOSCB_SGMIIPHY_LANE01_STRUCT;
171 
172 #define SGMIIPHY_LANE01_BASE  0x36500000UL
173 #define SGMIIPHY_LANE23_BASE  0x36510000UL
174 #define SGMIIPHY_LANE01  ((volatile IOSCB_SGMIIPHY_LANE01_STRUCT *) SGMIIPHY_LANE01_BASE)
175 #define SGMIIPHY_LANE23  ((volatile IOSCB_SGMIIPHY_LANE01_STRUCT *) SGMIIPHY_LANE23_BASE)
176 
177 
178 /**
179  * \brief GEM_A_LO GEM_B_LO
180  */
181 typedef struct IOSCB_GEM_X_LO_STRUCT_ {
182     __IO uint32_t network_control;      /* The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.  */
183     __IO uint32_t network_config;       /*             */
184     __IO uint32_t network_status;       /*             */
185     __IO uint32_t dma_config;           /*             */
186     __IO uint32_t transmit_status;      /*             */
187     __IO uint32_t receive_q_ptr;        /*             */
188 } IOSCB_GEM_X_LO_STRUCT;
189 
190 #define GEM_A_LO_BASE  0x20110004UL
191 #define GEM_B_LO_BASE  0x20112004UL
192 #define GEM_A_LO  ((volatile IOSCB_GEM_X_LO_STRUCT *) GEM_A_LO_BASE)
193 #define GEM_B_LO  ((volatile IOSCB_GEM_X_LO_STRUCT *) GEM_B_LO_BASE)
194 
195 /***************************************************************************//**
196 
197  */
198 typedef enum SGMII_TRAINING_SM_
199 {
200     SGMII_SETUP_INIT,                            /*!< SGMII_TRAINING_INIT */
201     SGMII_IO_EN,
202     SGMII_RAMP_TIMER,
203     SGMII_IO_SETUP,
204     SGMII_WAIT_FOR_CALIB_COMPLETE,
205     SGMII_ASSERT_CALIB_LOCK,
206     SGMII_SET_UP_PLL,
207     SGMII_WAIT_FOR_MSS_LOCK,
208     SGMII_WAIT_FOR_DLL_LOCK,
209     SGMII_TURN_ON_MACS,
210     SGMII_DETERMINE_SILICON_VARIANT,
211     SGMII_RESET_CHANNELS,
212     SGMII_WAIT_10MS,
213     SGMII_CHECK_REVC_RESULT,
214     SGMII_CHANNELS_UP
215 } SGMII_TRAINING_SM;
216 
217 #define SGMII_FINISHED_SETUP    0U
218 #define SGMII_IN_SETUP          1U
219 
220 
221 
222 /***************************************************************************//**
223   sgmii_off_mode() called in sgmii channels are not being used.
224 
225   Example:
226   @code
227 
228       sgmii_off_mode();
229 
230   @endcode
231 
232  */
233 void sgmii_off_mode(void);
234 
235 /***************************************************************************//**
236   sgmii_setup() sets up the SGMII using settings from Libero
237 
238   Example:
239   @code
240 
241       sgmii_setup();
242 
243   @endcode
244 
245  */
246 uint32_t sgmii_setup(void);
247 
248 /***************************************************************************//**
249   ddr_pvt_calibration() calibrates DDR I/O using the hardware function
250 
251   @return
252     This function returns status, see DDR_SS_STATUS enum
253 
254   Example:
255   @code
256 
257       ddr_pvt_calibration();
258 
259   @endcode
260 
261  */
262 void
263 ddr_pvt_calibration
264 (
265     void
266 );
267 
268 /***************************************************************************//**
269   ddr_pvt_recalibration() recalibrates DDR I/O using the hardware function
270 
271 
272   Example:
273   @code
274 
275       ddr_pvt_recalibration();
276 
277   @endcode
278 
279  */
280 void ddr_pvt_recalibration(void);
281 
282 #ifdef __cplusplus
283 }
284 #endif
285 
286 #endif /* SRC_PLATFORM_MPFS_HAL_NWC_MSS_SGMII_H_ */
287