1 /* 2 * Component description for TC 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:46Z */ 21 #ifndef _PIC32CXSG60_TC_COMPONENT_H_ 22 #define _PIC32CXSG60_TC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR TC */ 26 /* ************************************************************************** */ 27 28 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */ 29 #define TC_CTRLA_RESETVALUE _UINT32_(0x00) /* (TC_CTRLA) Control A Reset Value */ 30 31 #define TC_CTRLA_SWRST_Pos _UINT32_(0) /* (TC_CTRLA) Software Reset Position */ 32 #define TC_CTRLA_SWRST_Msk (_UINT32_(0x1) << TC_CTRLA_SWRST_Pos) /* (TC_CTRLA) Software Reset Mask */ 33 #define TC_CTRLA_SWRST(value) (TC_CTRLA_SWRST_Msk & (_UINT32_(value) << TC_CTRLA_SWRST_Pos)) /* Assigment of value for SWRST in the TC_CTRLA register */ 34 #define TC_CTRLA_ENABLE_Pos _UINT32_(1) /* (TC_CTRLA) Enable Position */ 35 #define TC_CTRLA_ENABLE_Msk (_UINT32_(0x1) << TC_CTRLA_ENABLE_Pos) /* (TC_CTRLA) Enable Mask */ 36 #define TC_CTRLA_ENABLE(value) (TC_CTRLA_ENABLE_Msk & (_UINT32_(value) << TC_CTRLA_ENABLE_Pos)) /* Assigment of value for ENABLE in the TC_CTRLA register */ 37 #define TC_CTRLA_MODE_Pos _UINT32_(2) /* (TC_CTRLA) Timer Counter Mode Position */ 38 #define TC_CTRLA_MODE_Msk (_UINT32_(0x3) << TC_CTRLA_MODE_Pos) /* (TC_CTRLA) Timer Counter Mode Mask */ 39 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & (_UINT32_(value) << TC_CTRLA_MODE_Pos)) /* Assigment of value for MODE in the TC_CTRLA register */ 40 #define TC_CTRLA_MODE_COUNT16_Val _UINT32_(0x0) /* (TC_CTRLA) Counter in 16-bit mode */ 41 #define TC_CTRLA_MODE_COUNT8_Val _UINT32_(0x1) /* (TC_CTRLA) Counter in 8-bit mode */ 42 #define TC_CTRLA_MODE_COUNT32_Val _UINT32_(0x2) /* (TC_CTRLA) Counter in 32-bit mode */ 43 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) /* (TC_CTRLA) Counter in 16-bit mode Position */ 44 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) /* (TC_CTRLA) Counter in 8-bit mode Position */ 45 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) /* (TC_CTRLA) Counter in 32-bit mode Position */ 46 #define TC_CTRLA_PRESCSYNC_Pos _UINT32_(4) /* (TC_CTRLA) Prescaler and Counter Synchronization Position */ 47 #define TC_CTRLA_PRESCSYNC_Msk (_UINT32_(0x3) << TC_CTRLA_PRESCSYNC_Pos) /* (TC_CTRLA) Prescaler and Counter Synchronization Mask */ 48 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & (_UINT32_(value) << TC_CTRLA_PRESCSYNC_Pos)) /* Assigment of value for PRESCSYNC in the TC_CTRLA register */ 49 #define TC_CTRLA_PRESCSYNC_GCLK_Val _UINT32_(0x0) /* (TC_CTRLA) Reload or reset the counter on next generic clock */ 50 #define TC_CTRLA_PRESCSYNC_PRESC_Val _UINT32_(0x1) /* (TC_CTRLA) Reload or reset the counter on next prescaler clock */ 51 #define TC_CTRLA_PRESCSYNC_RESYNC_Val _UINT32_(0x2) /* (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */ 52 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) /* (TC_CTRLA) Reload or reset the counter on next generic clock Position */ 53 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) /* (TC_CTRLA) Reload or reset the counter on next prescaler clock Position */ 54 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) /* (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter Position */ 55 #define TC_CTRLA_RUNSTDBY_Pos _UINT32_(6) /* (TC_CTRLA) Run during Standby Position */ 56 #define TC_CTRLA_RUNSTDBY_Msk (_UINT32_(0x1) << TC_CTRLA_RUNSTDBY_Pos) /* (TC_CTRLA) Run during Standby Mask */ 57 #define TC_CTRLA_RUNSTDBY(value) (TC_CTRLA_RUNSTDBY_Msk & (_UINT32_(value) << TC_CTRLA_RUNSTDBY_Pos)) /* Assigment of value for RUNSTDBY in the TC_CTRLA register */ 58 #define TC_CTRLA_ONDEMAND_Pos _UINT32_(7) /* (TC_CTRLA) Clock On Demand Position */ 59 #define TC_CTRLA_ONDEMAND_Msk (_UINT32_(0x1) << TC_CTRLA_ONDEMAND_Pos) /* (TC_CTRLA) Clock On Demand Mask */ 60 #define TC_CTRLA_ONDEMAND(value) (TC_CTRLA_ONDEMAND_Msk & (_UINT32_(value) << TC_CTRLA_ONDEMAND_Pos)) /* Assigment of value for ONDEMAND in the TC_CTRLA register */ 61 #define TC_CTRLA_PRESCALER_Pos _UINT32_(8) /* (TC_CTRLA) Prescaler Position */ 62 #define TC_CTRLA_PRESCALER_Msk (_UINT32_(0x7) << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler Mask */ 63 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & (_UINT32_(value) << TC_CTRLA_PRESCALER_Pos)) /* Assigment of value for PRESCALER in the TC_CTRLA register */ 64 #define TC_CTRLA_PRESCALER_DIV1_Val _UINT32_(0x0) /* (TC_CTRLA) Prescaler: GCLK_TC */ 65 #define TC_CTRLA_PRESCALER_DIV2_Val _UINT32_(0x1) /* (TC_CTRLA) Prescaler: GCLK_TC/2 */ 66 #define TC_CTRLA_PRESCALER_DIV4_Val _UINT32_(0x2) /* (TC_CTRLA) Prescaler: GCLK_TC/4 */ 67 #define TC_CTRLA_PRESCALER_DIV8_Val _UINT32_(0x3) /* (TC_CTRLA) Prescaler: GCLK_TC/8 */ 68 #define TC_CTRLA_PRESCALER_DIV16_Val _UINT32_(0x4) /* (TC_CTRLA) Prescaler: GCLK_TC/16 */ 69 #define TC_CTRLA_PRESCALER_DIV64_Val _UINT32_(0x5) /* (TC_CTRLA) Prescaler: GCLK_TC/64 */ 70 #define TC_CTRLA_PRESCALER_DIV256_Val _UINT32_(0x6) /* (TC_CTRLA) Prescaler: GCLK_TC/256 */ 71 #define TC_CTRLA_PRESCALER_DIV1024_Val _UINT32_(0x7) /* (TC_CTRLA) Prescaler: GCLK_TC/1024 */ 72 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC Position */ 73 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/2 Position */ 74 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/4 Position */ 75 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/8 Position */ 76 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/16 Position */ 77 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/64 Position */ 78 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/256 Position */ 79 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) /* (TC_CTRLA) Prescaler: GCLK_TC/1024 Position */ 80 #define TC_CTRLA_ALOCK_Pos _UINT32_(11) /* (TC_CTRLA) Auto Lock Position */ 81 #define TC_CTRLA_ALOCK_Msk (_UINT32_(0x1) << TC_CTRLA_ALOCK_Pos) /* (TC_CTRLA) Auto Lock Mask */ 82 #define TC_CTRLA_ALOCK(value) (TC_CTRLA_ALOCK_Msk & (_UINT32_(value) << TC_CTRLA_ALOCK_Pos)) /* Assigment of value for ALOCK in the TC_CTRLA register */ 83 #define TC_CTRLA_CAPTEN0_Pos _UINT32_(16) /* (TC_CTRLA) Capture Channel 0 Enable Position */ 84 #define TC_CTRLA_CAPTEN0_Msk (_UINT32_(0x1) << TC_CTRLA_CAPTEN0_Pos) /* (TC_CTRLA) Capture Channel 0 Enable Mask */ 85 #define TC_CTRLA_CAPTEN0(value) (TC_CTRLA_CAPTEN0_Msk & (_UINT32_(value) << TC_CTRLA_CAPTEN0_Pos)) /* Assigment of value for CAPTEN0 in the TC_CTRLA register */ 86 #define TC_CTRLA_CAPTEN1_Pos _UINT32_(17) /* (TC_CTRLA) Capture Channel 1 Enable Position */ 87 #define TC_CTRLA_CAPTEN1_Msk (_UINT32_(0x1) << TC_CTRLA_CAPTEN1_Pos) /* (TC_CTRLA) Capture Channel 1 Enable Mask */ 88 #define TC_CTRLA_CAPTEN1(value) (TC_CTRLA_CAPTEN1_Msk & (_UINT32_(value) << TC_CTRLA_CAPTEN1_Pos)) /* Assigment of value for CAPTEN1 in the TC_CTRLA register */ 89 #define TC_CTRLA_COPEN0_Pos _UINT32_(20) /* (TC_CTRLA) Capture On Pin 0 Enable Position */ 90 #define TC_CTRLA_COPEN0_Msk (_UINT32_(0x1) << TC_CTRLA_COPEN0_Pos) /* (TC_CTRLA) Capture On Pin 0 Enable Mask */ 91 #define TC_CTRLA_COPEN0(value) (TC_CTRLA_COPEN0_Msk & (_UINT32_(value) << TC_CTRLA_COPEN0_Pos)) /* Assigment of value for COPEN0 in the TC_CTRLA register */ 92 #define TC_CTRLA_COPEN1_Pos _UINT32_(21) /* (TC_CTRLA) Capture On Pin 1 Enable Position */ 93 #define TC_CTRLA_COPEN1_Msk (_UINT32_(0x1) << TC_CTRLA_COPEN1_Pos) /* (TC_CTRLA) Capture On Pin 1 Enable Mask */ 94 #define TC_CTRLA_COPEN1(value) (TC_CTRLA_COPEN1_Msk & (_UINT32_(value) << TC_CTRLA_COPEN1_Pos)) /* Assigment of value for COPEN1 in the TC_CTRLA register */ 95 #define TC_CTRLA_CAPTMODE0_Pos _UINT32_(24) /* (TC_CTRLA) Capture Mode Channel 0 Position */ 96 #define TC_CTRLA_CAPTMODE0_Msk (_UINT32_(0x3) << TC_CTRLA_CAPTMODE0_Pos) /* (TC_CTRLA) Capture Mode Channel 0 Mask */ 97 #define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & (_UINT32_(value) << TC_CTRLA_CAPTMODE0_Pos)) /* Assigment of value for CAPTMODE0 in the TC_CTRLA register */ 98 #define TC_CTRLA_CAPTMODE0_DEFAULT_Val _UINT32_(0x0) /* (TC_CTRLA) Default capture */ 99 #define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _UINT32_(0x1) /* (TC_CTRLA) Minimum capture */ 100 #define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _UINT32_(0x2) /* (TC_CTRLA) Maximum capture */ 101 #define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos) /* (TC_CTRLA) Default capture Position */ 102 #define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos) /* (TC_CTRLA) Minimum capture Position */ 103 #define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos) /* (TC_CTRLA) Maximum capture Position */ 104 #define TC_CTRLA_CAPTMODE1_Pos _UINT32_(27) /* (TC_CTRLA) Capture mode Channel 1 Position */ 105 #define TC_CTRLA_CAPTMODE1_Msk (_UINT32_(0x3) << TC_CTRLA_CAPTMODE1_Pos) /* (TC_CTRLA) Capture mode Channel 1 Mask */ 106 #define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & (_UINT32_(value) << TC_CTRLA_CAPTMODE1_Pos)) /* Assigment of value for CAPTMODE1 in the TC_CTRLA register */ 107 #define TC_CTRLA_CAPTMODE1_DEFAULT_Val _UINT32_(0x0) /* (TC_CTRLA) Default capture */ 108 #define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _UINT32_(0x1) /* (TC_CTRLA) Minimum capture */ 109 #define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _UINT32_(0x2) /* (TC_CTRLA) Maximum capture */ 110 #define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos) /* (TC_CTRLA) Default capture Position */ 111 #define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos) /* (TC_CTRLA) Minimum capture Position */ 112 #define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos) /* (TC_CTRLA) Maximum capture Position */ 113 #define TC_CTRLA_Msk _UINT32_(0x1B330FFF) /* (TC_CTRLA) Register Mask */ 114 115 #define TC_CTRLA_CAPTEN_Pos _UINT32_(16) /* (TC_CTRLA Position) Capture Channel x Enable */ 116 #define TC_CTRLA_CAPTEN_Msk (_UINT32_(0x3) << TC_CTRLA_CAPTEN_Pos) /* (TC_CTRLA Mask) CAPTEN */ 117 #define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & (_UINT32_(value) << TC_CTRLA_CAPTEN_Pos)) 118 #define TC_CTRLA_COPEN_Pos _UINT32_(20) /* (TC_CTRLA Position) Capture On Pin x Enable */ 119 #define TC_CTRLA_COPEN_Msk (_UINT32_(0x3) << TC_CTRLA_COPEN_Pos) /* (TC_CTRLA Mask) COPEN */ 120 #define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & (_UINT32_(value) << TC_CTRLA_COPEN_Pos)) 121 122 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ 123 #define TC_CTRLBCLR_RESETVALUE _UINT8_(0x00) /* (TC_CTRLBCLR) Control B Clear Reset Value */ 124 125 #define TC_CTRLBCLR_DIR_Pos _UINT8_(0) /* (TC_CTRLBCLR) Counter Direction Position */ 126 #define TC_CTRLBCLR_DIR_Msk (_UINT8_(0x1) << TC_CTRLBCLR_DIR_Pos) /* (TC_CTRLBCLR) Counter Direction Mask */ 127 #define TC_CTRLBCLR_DIR(value) (TC_CTRLBCLR_DIR_Msk & (_UINT8_(value) << TC_CTRLBCLR_DIR_Pos)) /* Assigment of value for DIR in the TC_CTRLBCLR register */ 128 #define TC_CTRLBCLR_LUPD_Pos _UINT8_(1) /* (TC_CTRLBCLR) Lock Update Position */ 129 #define TC_CTRLBCLR_LUPD_Msk (_UINT8_(0x1) << TC_CTRLBCLR_LUPD_Pos) /* (TC_CTRLBCLR) Lock Update Mask */ 130 #define TC_CTRLBCLR_LUPD(value) (TC_CTRLBCLR_LUPD_Msk & (_UINT8_(value) << TC_CTRLBCLR_LUPD_Pos)) /* Assigment of value for LUPD in the TC_CTRLBCLR register */ 131 #define TC_CTRLBCLR_ONESHOT_Pos _UINT8_(2) /* (TC_CTRLBCLR) One-Shot on Counter Position */ 132 #define TC_CTRLBCLR_ONESHOT_Msk (_UINT8_(0x1) << TC_CTRLBCLR_ONESHOT_Pos) /* (TC_CTRLBCLR) One-Shot on Counter Mask */ 133 #define TC_CTRLBCLR_ONESHOT(value) (TC_CTRLBCLR_ONESHOT_Msk & (_UINT8_(value) << TC_CTRLBCLR_ONESHOT_Pos)) /* Assigment of value for ONESHOT in the TC_CTRLBCLR register */ 134 #define TC_CTRLBCLR_CMD_Pos _UINT8_(5) /* (TC_CTRLBCLR) Command Position */ 135 #define TC_CTRLBCLR_CMD_Msk (_UINT8_(0x7) << TC_CTRLBCLR_CMD_Pos) /* (TC_CTRLBCLR) Command Mask */ 136 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & (_UINT8_(value) << TC_CTRLBCLR_CMD_Pos)) /* Assigment of value for CMD in the TC_CTRLBCLR register */ 137 #define TC_CTRLBCLR_CMD_NONE_Val _UINT8_(0x0) /* (TC_CTRLBCLR) No action */ 138 #define TC_CTRLBCLR_CMD_RETRIGGER_Val _UINT8_(0x1) /* (TC_CTRLBCLR) Force a start, restart or retrigger */ 139 #define TC_CTRLBCLR_CMD_STOP_Val _UINT8_(0x2) /* (TC_CTRLBCLR) Force a stop */ 140 #define TC_CTRLBCLR_CMD_UPDATE_Val _UINT8_(0x3) /* (TC_CTRLBCLR) Force update of double-buffered register */ 141 #define TC_CTRLBCLR_CMD_READSYNC_Val _UINT8_(0x4) /* (TC_CTRLBCLR) Force a read synchronization of COUNT */ 142 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) /* (TC_CTRLBCLR) No action Position */ 143 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) /* (TC_CTRLBCLR) Force a start, restart or retrigger Position */ 144 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) /* (TC_CTRLBCLR) Force a stop Position */ 145 #define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos) /* (TC_CTRLBCLR) Force update of double-buffered register Position */ 146 #define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos) /* (TC_CTRLBCLR) Force a read synchronization of COUNT Position */ 147 #define TC_CTRLBCLR_Msk _UINT8_(0xE7) /* (TC_CTRLBCLR) Register Mask */ 148 149 150 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ 151 #define TC_CTRLBSET_RESETVALUE _UINT8_(0x00) /* (TC_CTRLBSET) Control B Set Reset Value */ 152 153 #define TC_CTRLBSET_DIR_Pos _UINT8_(0) /* (TC_CTRLBSET) Counter Direction Position */ 154 #define TC_CTRLBSET_DIR_Msk (_UINT8_(0x1) << TC_CTRLBSET_DIR_Pos) /* (TC_CTRLBSET) Counter Direction Mask */ 155 #define TC_CTRLBSET_DIR(value) (TC_CTRLBSET_DIR_Msk & (_UINT8_(value) << TC_CTRLBSET_DIR_Pos)) /* Assigment of value for DIR in the TC_CTRLBSET register */ 156 #define TC_CTRLBSET_LUPD_Pos _UINT8_(1) /* (TC_CTRLBSET) Lock Update Position */ 157 #define TC_CTRLBSET_LUPD_Msk (_UINT8_(0x1) << TC_CTRLBSET_LUPD_Pos) /* (TC_CTRLBSET) Lock Update Mask */ 158 #define TC_CTRLBSET_LUPD(value) (TC_CTRLBSET_LUPD_Msk & (_UINT8_(value) << TC_CTRLBSET_LUPD_Pos)) /* Assigment of value for LUPD in the TC_CTRLBSET register */ 159 #define TC_CTRLBSET_ONESHOT_Pos _UINT8_(2) /* (TC_CTRLBSET) One-Shot on Counter Position */ 160 #define TC_CTRLBSET_ONESHOT_Msk (_UINT8_(0x1) << TC_CTRLBSET_ONESHOT_Pos) /* (TC_CTRLBSET) One-Shot on Counter Mask */ 161 #define TC_CTRLBSET_ONESHOT(value) (TC_CTRLBSET_ONESHOT_Msk & (_UINT8_(value) << TC_CTRLBSET_ONESHOT_Pos)) /* Assigment of value for ONESHOT in the TC_CTRLBSET register */ 162 #define TC_CTRLBSET_CMD_Pos _UINT8_(5) /* (TC_CTRLBSET) Command Position */ 163 #define TC_CTRLBSET_CMD_Msk (_UINT8_(0x7) << TC_CTRLBSET_CMD_Pos) /* (TC_CTRLBSET) Command Mask */ 164 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & (_UINT8_(value) << TC_CTRLBSET_CMD_Pos)) /* Assigment of value for CMD in the TC_CTRLBSET register */ 165 #define TC_CTRLBSET_CMD_NONE_Val _UINT8_(0x0) /* (TC_CTRLBSET) No action */ 166 #define TC_CTRLBSET_CMD_RETRIGGER_Val _UINT8_(0x1) /* (TC_CTRLBSET) Force a start, restart or retrigger */ 167 #define TC_CTRLBSET_CMD_STOP_Val _UINT8_(0x2) /* (TC_CTRLBSET) Force a stop */ 168 #define TC_CTRLBSET_CMD_UPDATE_Val _UINT8_(0x3) /* (TC_CTRLBSET) Force update of double-buffered register */ 169 #define TC_CTRLBSET_CMD_READSYNC_Val _UINT8_(0x4) /* (TC_CTRLBSET) Force a read synchronization of COUNT */ 170 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) /* (TC_CTRLBSET) No action Position */ 171 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) /* (TC_CTRLBSET) Force a start, restart or retrigger Position */ 172 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) /* (TC_CTRLBSET) Force a stop Position */ 173 #define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos) /* (TC_CTRLBSET) Force update of double-buffered register Position */ 174 #define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos) /* (TC_CTRLBSET) Force a read synchronization of COUNT Position */ 175 #define TC_CTRLBSET_Msk _UINT8_(0xE7) /* (TC_CTRLBSET) Register Mask */ 176 177 178 /* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */ 179 #define TC_EVCTRL_RESETVALUE _UINT16_(0x00) /* (TC_EVCTRL) Event Control Reset Value */ 180 181 #define TC_EVCTRL_EVACT_Pos _UINT16_(0) /* (TC_EVCTRL) Event Action Position */ 182 #define TC_EVCTRL_EVACT_Msk (_UINT16_(0x7) << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Event Action Mask */ 183 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & (_UINT16_(value) << TC_EVCTRL_EVACT_Pos)) /* Assigment of value for EVACT in the TC_EVCTRL register */ 184 #define TC_EVCTRL_EVACT_OFF_Val _UINT16_(0x0) /* (TC_EVCTRL) Event action disabled */ 185 #define TC_EVCTRL_EVACT_RETRIGGER_Val _UINT16_(0x1) /* (TC_EVCTRL) Start, restart or retrigger TC on event */ 186 #define TC_EVCTRL_EVACT_COUNT_Val _UINT16_(0x2) /* (TC_EVCTRL) Count on event */ 187 #define TC_EVCTRL_EVACT_START_Val _UINT16_(0x3) /* (TC_EVCTRL) Start TC on event */ 188 #define TC_EVCTRL_EVACT_STAMP_Val _UINT16_(0x4) /* (TC_EVCTRL) Time stamp capture */ 189 #define TC_EVCTRL_EVACT_PPW_Val _UINT16_(0x5) /* (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */ 190 #define TC_EVCTRL_EVACT_PWP_Val _UINT16_(0x6) /* (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */ 191 #define TC_EVCTRL_EVACT_PW_Val _UINT16_(0x7) /* (TC_EVCTRL) Pulse width capture */ 192 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Event action disabled Position */ 193 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Start, restart or retrigger TC on event Position */ 194 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Count on event Position */ 195 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Start TC on event Position */ 196 #define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Time stamp capture Position */ 197 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Period catured in CC0, pulse width in CC1 Position */ 198 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Period catured in CC1, pulse width in CC0 Position */ 199 #define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos) /* (TC_EVCTRL) Pulse width capture Position */ 200 #define TC_EVCTRL_TCINV_Pos _UINT16_(4) /* (TC_EVCTRL) TC Event Input Polarity Position */ 201 #define TC_EVCTRL_TCINV_Msk (_UINT16_(0x1) << TC_EVCTRL_TCINV_Pos) /* (TC_EVCTRL) TC Event Input Polarity Mask */ 202 #define TC_EVCTRL_TCINV(value) (TC_EVCTRL_TCINV_Msk & (_UINT16_(value) << TC_EVCTRL_TCINV_Pos)) /* Assigment of value for TCINV in the TC_EVCTRL register */ 203 #define TC_EVCTRL_TCEI_Pos _UINT16_(5) /* (TC_EVCTRL) TC Event Enable Position */ 204 #define TC_EVCTRL_TCEI_Msk (_UINT16_(0x1) << TC_EVCTRL_TCEI_Pos) /* (TC_EVCTRL) TC Event Enable Mask */ 205 #define TC_EVCTRL_TCEI(value) (TC_EVCTRL_TCEI_Msk & (_UINT16_(value) << TC_EVCTRL_TCEI_Pos)) /* Assigment of value for TCEI in the TC_EVCTRL register */ 206 #define TC_EVCTRL_OVFEO_Pos _UINT16_(8) /* (TC_EVCTRL) Event Output Enable Position */ 207 #define TC_EVCTRL_OVFEO_Msk (_UINT16_(0x1) << TC_EVCTRL_OVFEO_Pos) /* (TC_EVCTRL) Event Output Enable Mask */ 208 #define TC_EVCTRL_OVFEO(value) (TC_EVCTRL_OVFEO_Msk & (_UINT16_(value) << TC_EVCTRL_OVFEO_Pos)) /* Assigment of value for OVFEO in the TC_EVCTRL register */ 209 #define TC_EVCTRL_MCEO0_Pos _UINT16_(12) /* (TC_EVCTRL) MC Event Output Enable 0 Position */ 210 #define TC_EVCTRL_MCEO0_Msk (_UINT16_(0x1) << TC_EVCTRL_MCEO0_Pos) /* (TC_EVCTRL) MC Event Output Enable 0 Mask */ 211 #define TC_EVCTRL_MCEO0(value) (TC_EVCTRL_MCEO0_Msk & (_UINT16_(value) << TC_EVCTRL_MCEO0_Pos)) /* Assigment of value for MCEO0 in the TC_EVCTRL register */ 212 #define TC_EVCTRL_MCEO1_Pos _UINT16_(13) /* (TC_EVCTRL) MC Event Output Enable 1 Position */ 213 #define TC_EVCTRL_MCEO1_Msk (_UINT16_(0x1) << TC_EVCTRL_MCEO1_Pos) /* (TC_EVCTRL) MC Event Output Enable 1 Mask */ 214 #define TC_EVCTRL_MCEO1(value) (TC_EVCTRL_MCEO1_Msk & (_UINT16_(value) << TC_EVCTRL_MCEO1_Pos)) /* Assigment of value for MCEO1 in the TC_EVCTRL register */ 215 #define TC_EVCTRL_Msk _UINT16_(0x3137) /* (TC_EVCTRL) Register Mask */ 216 217 #define TC_EVCTRL_MCEO_Pos _UINT16_(12) /* (TC_EVCTRL Position) MC Event Output Enable x */ 218 #define TC_EVCTRL_MCEO_Msk (_UINT16_(0x3) << TC_EVCTRL_MCEO_Pos) /* (TC_EVCTRL Mask) MCEO */ 219 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & (_UINT16_(value) << TC_EVCTRL_MCEO_Pos)) 220 221 /* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 222 #define TC_INTENCLR_RESETVALUE _UINT8_(0x00) /* (TC_INTENCLR) Interrupt Enable Clear Reset Value */ 223 224 #define TC_INTENCLR_OVF_Pos _UINT8_(0) /* (TC_INTENCLR) OVF Interrupt Disable Position */ 225 #define TC_INTENCLR_OVF_Msk (_UINT8_(0x1) << TC_INTENCLR_OVF_Pos) /* (TC_INTENCLR) OVF Interrupt Disable Mask */ 226 #define TC_INTENCLR_OVF(value) (TC_INTENCLR_OVF_Msk & (_UINT8_(value) << TC_INTENCLR_OVF_Pos)) /* Assigment of value for OVF in the TC_INTENCLR register */ 227 #define TC_INTENCLR_ERR_Pos _UINT8_(1) /* (TC_INTENCLR) ERR Interrupt Disable Position */ 228 #define TC_INTENCLR_ERR_Msk (_UINT8_(0x1) << TC_INTENCLR_ERR_Pos) /* (TC_INTENCLR) ERR Interrupt Disable Mask */ 229 #define TC_INTENCLR_ERR(value) (TC_INTENCLR_ERR_Msk & (_UINT8_(value) << TC_INTENCLR_ERR_Pos)) /* Assigment of value for ERR in the TC_INTENCLR register */ 230 #define TC_INTENCLR_MC0_Pos _UINT8_(4) /* (TC_INTENCLR) MC Interrupt Disable 0 Position */ 231 #define TC_INTENCLR_MC0_Msk (_UINT8_(0x1) << TC_INTENCLR_MC0_Pos) /* (TC_INTENCLR) MC Interrupt Disable 0 Mask */ 232 #define TC_INTENCLR_MC0(value) (TC_INTENCLR_MC0_Msk & (_UINT8_(value) << TC_INTENCLR_MC0_Pos)) /* Assigment of value for MC0 in the TC_INTENCLR register */ 233 #define TC_INTENCLR_MC1_Pos _UINT8_(5) /* (TC_INTENCLR) MC Interrupt Disable 1 Position */ 234 #define TC_INTENCLR_MC1_Msk (_UINT8_(0x1) << TC_INTENCLR_MC1_Pos) /* (TC_INTENCLR) MC Interrupt Disable 1 Mask */ 235 #define TC_INTENCLR_MC1(value) (TC_INTENCLR_MC1_Msk & (_UINT8_(value) << TC_INTENCLR_MC1_Pos)) /* Assigment of value for MC1 in the TC_INTENCLR register */ 236 #define TC_INTENCLR_Msk _UINT8_(0x33) /* (TC_INTENCLR) Register Mask */ 237 238 #define TC_INTENCLR_MC_Pos _UINT8_(4) /* (TC_INTENCLR Position) MC Interrupt Disable x */ 239 #define TC_INTENCLR_MC_Msk (_UINT8_(0x3) << TC_INTENCLR_MC_Pos) /* (TC_INTENCLR Mask) MC */ 240 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & (_UINT8_(value) << TC_INTENCLR_MC_Pos)) 241 242 /* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 243 #define TC_INTENSET_RESETVALUE _UINT8_(0x00) /* (TC_INTENSET) Interrupt Enable Set Reset Value */ 244 245 #define TC_INTENSET_OVF_Pos _UINT8_(0) /* (TC_INTENSET) OVF Interrupt Enable Position */ 246 #define TC_INTENSET_OVF_Msk (_UINT8_(0x1) << TC_INTENSET_OVF_Pos) /* (TC_INTENSET) OVF Interrupt Enable Mask */ 247 #define TC_INTENSET_OVF(value) (TC_INTENSET_OVF_Msk & (_UINT8_(value) << TC_INTENSET_OVF_Pos)) /* Assigment of value for OVF in the TC_INTENSET register */ 248 #define TC_INTENSET_ERR_Pos _UINT8_(1) /* (TC_INTENSET) ERR Interrupt Enable Position */ 249 #define TC_INTENSET_ERR_Msk (_UINT8_(0x1) << TC_INTENSET_ERR_Pos) /* (TC_INTENSET) ERR Interrupt Enable Mask */ 250 #define TC_INTENSET_ERR(value) (TC_INTENSET_ERR_Msk & (_UINT8_(value) << TC_INTENSET_ERR_Pos)) /* Assigment of value for ERR in the TC_INTENSET register */ 251 #define TC_INTENSET_MC0_Pos _UINT8_(4) /* (TC_INTENSET) MC Interrupt Enable 0 Position */ 252 #define TC_INTENSET_MC0_Msk (_UINT8_(0x1) << TC_INTENSET_MC0_Pos) /* (TC_INTENSET) MC Interrupt Enable 0 Mask */ 253 #define TC_INTENSET_MC0(value) (TC_INTENSET_MC0_Msk & (_UINT8_(value) << TC_INTENSET_MC0_Pos)) /* Assigment of value for MC0 in the TC_INTENSET register */ 254 #define TC_INTENSET_MC1_Pos _UINT8_(5) /* (TC_INTENSET) MC Interrupt Enable 1 Position */ 255 #define TC_INTENSET_MC1_Msk (_UINT8_(0x1) << TC_INTENSET_MC1_Pos) /* (TC_INTENSET) MC Interrupt Enable 1 Mask */ 256 #define TC_INTENSET_MC1(value) (TC_INTENSET_MC1_Msk & (_UINT8_(value) << TC_INTENSET_MC1_Pos)) /* Assigment of value for MC1 in the TC_INTENSET register */ 257 #define TC_INTENSET_Msk _UINT8_(0x33) /* (TC_INTENSET) Register Mask */ 258 259 #define TC_INTENSET_MC_Pos _UINT8_(4) /* (TC_INTENSET Position) MC Interrupt Enable x */ 260 #define TC_INTENSET_MC_Msk (_UINT8_(0x3) << TC_INTENSET_MC_Pos) /* (TC_INTENSET Mask) MC */ 261 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & (_UINT8_(value) << TC_INTENSET_MC_Pos)) 262 263 /* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 264 #define TC_INTFLAG_RESETVALUE _UINT8_(0x00) /* (TC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 265 266 #define TC_INTFLAG_OVF_Pos _UINT8_(0) /* (TC_INTFLAG) OVF Interrupt Flag Position */ 267 #define TC_INTFLAG_OVF_Msk (_UINT8_(0x1) << TC_INTFLAG_OVF_Pos) /* (TC_INTFLAG) OVF Interrupt Flag Mask */ 268 #define TC_INTFLAG_OVF(value) (TC_INTFLAG_OVF_Msk & (_UINT8_(value) << TC_INTFLAG_OVF_Pos)) /* Assigment of value for OVF in the TC_INTFLAG register */ 269 #define TC_INTFLAG_ERR_Pos _UINT8_(1) /* (TC_INTFLAG) ERR Interrupt Flag Position */ 270 #define TC_INTFLAG_ERR_Msk (_UINT8_(0x1) << TC_INTFLAG_ERR_Pos) /* (TC_INTFLAG) ERR Interrupt Flag Mask */ 271 #define TC_INTFLAG_ERR(value) (TC_INTFLAG_ERR_Msk & (_UINT8_(value) << TC_INTFLAG_ERR_Pos)) /* Assigment of value for ERR in the TC_INTFLAG register */ 272 #define TC_INTFLAG_MC0_Pos _UINT8_(4) /* (TC_INTFLAG) MC Interrupt Flag 0 Position */ 273 #define TC_INTFLAG_MC0_Msk (_UINT8_(0x1) << TC_INTFLAG_MC0_Pos) /* (TC_INTFLAG) MC Interrupt Flag 0 Mask */ 274 #define TC_INTFLAG_MC0(value) (TC_INTFLAG_MC0_Msk & (_UINT8_(value) << TC_INTFLAG_MC0_Pos)) /* Assigment of value for MC0 in the TC_INTFLAG register */ 275 #define TC_INTFLAG_MC1_Pos _UINT8_(5) /* (TC_INTFLAG) MC Interrupt Flag 1 Position */ 276 #define TC_INTFLAG_MC1_Msk (_UINT8_(0x1) << TC_INTFLAG_MC1_Pos) /* (TC_INTFLAG) MC Interrupt Flag 1 Mask */ 277 #define TC_INTFLAG_MC1(value) (TC_INTFLAG_MC1_Msk & (_UINT8_(value) << TC_INTFLAG_MC1_Pos)) /* Assigment of value for MC1 in the TC_INTFLAG register */ 278 #define TC_INTFLAG_Msk _UINT8_(0x33) /* (TC_INTFLAG) Register Mask */ 279 280 #define TC_INTFLAG_MC_Pos _UINT8_(4) /* (TC_INTFLAG Position) MC Interrupt Flag x */ 281 #define TC_INTFLAG_MC_Msk (_UINT8_(0x3) << TC_INTFLAG_MC_Pos) /* (TC_INTFLAG Mask) MC */ 282 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & (_UINT8_(value) << TC_INTFLAG_MC_Pos)) 283 284 /* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */ 285 #define TC_STATUS_RESETVALUE _UINT8_(0x01) /* (TC_STATUS) Status Reset Value */ 286 287 #define TC_STATUS_STOP_Pos _UINT8_(0) /* (TC_STATUS) Stop Status Flag Position */ 288 #define TC_STATUS_STOP_Msk (_UINT8_(0x1) << TC_STATUS_STOP_Pos) /* (TC_STATUS) Stop Status Flag Mask */ 289 #define TC_STATUS_STOP(value) (TC_STATUS_STOP_Msk & (_UINT8_(value) << TC_STATUS_STOP_Pos)) /* Assigment of value for STOP in the TC_STATUS register */ 290 #define TC_STATUS_SLAVE_Pos _UINT8_(1) /* (TC_STATUS) Slave Status Flag Position */ 291 #define TC_STATUS_SLAVE_Msk (_UINT8_(0x1) << TC_STATUS_SLAVE_Pos) /* (TC_STATUS) Slave Status Flag Mask */ 292 #define TC_STATUS_SLAVE(value) (TC_STATUS_SLAVE_Msk & (_UINT8_(value) << TC_STATUS_SLAVE_Pos)) /* Assigment of value for SLAVE in the TC_STATUS register */ 293 #define TC_STATUS_PERBUFV_Pos _UINT8_(3) /* (TC_STATUS) Synchronization Busy Status Position */ 294 #define TC_STATUS_PERBUFV_Msk (_UINT8_(0x1) << TC_STATUS_PERBUFV_Pos) /* (TC_STATUS) Synchronization Busy Status Mask */ 295 #define TC_STATUS_PERBUFV(value) (TC_STATUS_PERBUFV_Msk & (_UINT8_(value) << TC_STATUS_PERBUFV_Pos)) /* Assigment of value for PERBUFV in the TC_STATUS register */ 296 #define TC_STATUS_CCBUFV0_Pos _UINT8_(4) /* (TC_STATUS) Compare channel buffer 0 valid Position */ 297 #define TC_STATUS_CCBUFV0_Msk (_UINT8_(0x1) << TC_STATUS_CCBUFV0_Pos) /* (TC_STATUS) Compare channel buffer 0 valid Mask */ 298 #define TC_STATUS_CCBUFV0(value) (TC_STATUS_CCBUFV0_Msk & (_UINT8_(value) << TC_STATUS_CCBUFV0_Pos)) /* Assigment of value for CCBUFV0 in the TC_STATUS register */ 299 #define TC_STATUS_CCBUFV1_Pos _UINT8_(5) /* (TC_STATUS) Compare channel buffer 1 valid Position */ 300 #define TC_STATUS_CCBUFV1_Msk (_UINT8_(0x1) << TC_STATUS_CCBUFV1_Pos) /* (TC_STATUS) Compare channel buffer 1 valid Mask */ 301 #define TC_STATUS_CCBUFV1(value) (TC_STATUS_CCBUFV1_Msk & (_UINT8_(value) << TC_STATUS_CCBUFV1_Pos)) /* Assigment of value for CCBUFV1 in the TC_STATUS register */ 302 #define TC_STATUS_Msk _UINT8_(0x3B) /* (TC_STATUS) Register Mask */ 303 304 #define TC_STATUS_CCBUFV_Pos _UINT8_(4) /* (TC_STATUS Position) Compare channel buffer x valid */ 305 #define TC_STATUS_CCBUFV_Msk (_UINT8_(0x3) << TC_STATUS_CCBUFV_Pos) /* (TC_STATUS Mask) CCBUFV */ 306 #define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & (_UINT8_(value) << TC_STATUS_CCBUFV_Pos)) 307 308 /* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */ 309 #define TC_WAVE_RESETVALUE _UINT8_(0x00) /* (TC_WAVE) Waveform Generation Control Reset Value */ 310 311 #define TC_WAVE_WAVEGEN_Pos _UINT8_(0) /* (TC_WAVE) Waveform Generation Mode Position */ 312 #define TC_WAVE_WAVEGEN_Msk (_UINT8_(0x3) << TC_WAVE_WAVEGEN_Pos) /* (TC_WAVE) Waveform Generation Mode Mask */ 313 #define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & (_UINT8_(value) << TC_WAVE_WAVEGEN_Pos)) /* Assigment of value for WAVEGEN in the TC_WAVE register */ 314 #define TC_WAVE_WAVEGEN_NFRQ_Val _UINT8_(0x0) /* (TC_WAVE) Normal frequency */ 315 #define TC_WAVE_WAVEGEN_MFRQ_Val _UINT8_(0x1) /* (TC_WAVE) Match frequency */ 316 #define TC_WAVE_WAVEGEN_NPWM_Val _UINT8_(0x2) /* (TC_WAVE) Normal PWM */ 317 #define TC_WAVE_WAVEGEN_MPWM_Val _UINT8_(0x3) /* (TC_WAVE) Match PWM */ 318 #define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos) /* (TC_WAVE) Normal frequency Position */ 319 #define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos) /* (TC_WAVE) Match frequency Position */ 320 #define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos) /* (TC_WAVE) Normal PWM Position */ 321 #define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos) /* (TC_WAVE) Match PWM Position */ 322 #define TC_WAVE_Msk _UINT8_(0x03) /* (TC_WAVE) Register Mask */ 323 324 325 /* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */ 326 #define TC_DRVCTRL_RESETVALUE _UINT8_(0x00) /* (TC_DRVCTRL) Control C Reset Value */ 327 328 #define TC_DRVCTRL_INVEN0_Pos _UINT8_(0) /* (TC_DRVCTRL) Output Waveform Invert Enable 0 Position */ 329 #define TC_DRVCTRL_INVEN0_Msk (_UINT8_(0x1) << TC_DRVCTRL_INVEN0_Pos) /* (TC_DRVCTRL) Output Waveform Invert Enable 0 Mask */ 330 #define TC_DRVCTRL_INVEN0(value) (TC_DRVCTRL_INVEN0_Msk & (_UINT8_(value) << TC_DRVCTRL_INVEN0_Pos)) /* Assigment of value for INVEN0 in the TC_DRVCTRL register */ 331 #define TC_DRVCTRL_INVEN1_Pos _UINT8_(1) /* (TC_DRVCTRL) Output Waveform Invert Enable 1 Position */ 332 #define TC_DRVCTRL_INVEN1_Msk (_UINT8_(0x1) << TC_DRVCTRL_INVEN1_Pos) /* (TC_DRVCTRL) Output Waveform Invert Enable 1 Mask */ 333 #define TC_DRVCTRL_INVEN1(value) (TC_DRVCTRL_INVEN1_Msk & (_UINT8_(value) << TC_DRVCTRL_INVEN1_Pos)) /* Assigment of value for INVEN1 in the TC_DRVCTRL register */ 334 #define TC_DRVCTRL_Msk _UINT8_(0x03) /* (TC_DRVCTRL) Register Mask */ 335 336 #define TC_DRVCTRL_INVEN_Pos _UINT8_(0) /* (TC_DRVCTRL Position) Output Waveform Invert Enable x */ 337 #define TC_DRVCTRL_INVEN_Msk (_UINT8_(0x3) << TC_DRVCTRL_INVEN_Pos) /* (TC_DRVCTRL Mask) INVEN */ 338 #define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & (_UINT8_(value) << TC_DRVCTRL_INVEN_Pos)) 339 340 /* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */ 341 #define TC_DBGCTRL_RESETVALUE _UINT8_(0x00) /* (TC_DBGCTRL) Debug Control Reset Value */ 342 343 #define TC_DBGCTRL_DBGRUN_Pos _UINT8_(0) /* (TC_DBGCTRL) Run During Debug Position */ 344 #define TC_DBGCTRL_DBGRUN_Msk (_UINT8_(0x1) << TC_DBGCTRL_DBGRUN_Pos) /* (TC_DBGCTRL) Run During Debug Mask */ 345 #define TC_DBGCTRL_DBGRUN(value) (TC_DBGCTRL_DBGRUN_Msk & (_UINT8_(value) << TC_DBGCTRL_DBGRUN_Pos)) /* Assigment of value for DBGRUN in the TC_DBGCTRL register */ 346 #define TC_DBGCTRL_Msk _UINT8_(0x01) /* (TC_DBGCTRL) Register Mask */ 347 348 349 /* -------- TC_SYNCBUSY : (TC Offset: 0x10) ( R/ 32) Synchronization Status -------- */ 350 #define TC_SYNCBUSY_RESETVALUE _UINT32_(0x00) /* (TC_SYNCBUSY) Synchronization Status Reset Value */ 351 352 #define TC_SYNCBUSY_SWRST_Pos _UINT32_(0) /* (TC_SYNCBUSY) swrst Position */ 353 #define TC_SYNCBUSY_SWRST_Msk (_UINT32_(0x1) << TC_SYNCBUSY_SWRST_Pos) /* (TC_SYNCBUSY) swrst Mask */ 354 #define TC_SYNCBUSY_SWRST(value) (TC_SYNCBUSY_SWRST_Msk & (_UINT32_(value) << TC_SYNCBUSY_SWRST_Pos)) /* Assigment of value for SWRST in the TC_SYNCBUSY register */ 355 #define TC_SYNCBUSY_ENABLE_Pos _UINT32_(1) /* (TC_SYNCBUSY) enable Position */ 356 #define TC_SYNCBUSY_ENABLE_Msk (_UINT32_(0x1) << TC_SYNCBUSY_ENABLE_Pos) /* (TC_SYNCBUSY) enable Mask */ 357 #define TC_SYNCBUSY_ENABLE(value) (TC_SYNCBUSY_ENABLE_Msk & (_UINT32_(value) << TC_SYNCBUSY_ENABLE_Pos)) /* Assigment of value for ENABLE in the TC_SYNCBUSY register */ 358 #define TC_SYNCBUSY_CTRLB_Pos _UINT32_(2) /* (TC_SYNCBUSY) CTRLB Position */ 359 #define TC_SYNCBUSY_CTRLB_Msk (_UINT32_(0x1) << TC_SYNCBUSY_CTRLB_Pos) /* (TC_SYNCBUSY) CTRLB Mask */ 360 #define TC_SYNCBUSY_CTRLB(value) (TC_SYNCBUSY_CTRLB_Msk & (_UINT32_(value) << TC_SYNCBUSY_CTRLB_Pos)) /* Assigment of value for CTRLB in the TC_SYNCBUSY register */ 361 #define TC_SYNCBUSY_STATUS_Pos _UINT32_(3) /* (TC_SYNCBUSY) STATUS Position */ 362 #define TC_SYNCBUSY_STATUS_Msk (_UINT32_(0x1) << TC_SYNCBUSY_STATUS_Pos) /* (TC_SYNCBUSY) STATUS Mask */ 363 #define TC_SYNCBUSY_STATUS(value) (TC_SYNCBUSY_STATUS_Msk & (_UINT32_(value) << TC_SYNCBUSY_STATUS_Pos)) /* Assigment of value for STATUS in the TC_SYNCBUSY register */ 364 #define TC_SYNCBUSY_COUNT_Pos _UINT32_(4) /* (TC_SYNCBUSY) Counter Position */ 365 #define TC_SYNCBUSY_COUNT_Msk (_UINT32_(0x1) << TC_SYNCBUSY_COUNT_Pos) /* (TC_SYNCBUSY) Counter Mask */ 366 #define TC_SYNCBUSY_COUNT(value) (TC_SYNCBUSY_COUNT_Msk & (_UINT32_(value) << TC_SYNCBUSY_COUNT_Pos)) /* Assigment of value for COUNT in the TC_SYNCBUSY register */ 367 #define TC_SYNCBUSY_PER_Pos _UINT32_(5) /* (TC_SYNCBUSY) Period Position */ 368 #define TC_SYNCBUSY_PER_Msk (_UINT32_(0x1) << TC_SYNCBUSY_PER_Pos) /* (TC_SYNCBUSY) Period Mask */ 369 #define TC_SYNCBUSY_PER(value) (TC_SYNCBUSY_PER_Msk & (_UINT32_(value) << TC_SYNCBUSY_PER_Pos)) /* Assigment of value for PER in the TC_SYNCBUSY register */ 370 #define TC_SYNCBUSY_CC0_Pos _UINT32_(6) /* (TC_SYNCBUSY) Compare Channel 0 Position */ 371 #define TC_SYNCBUSY_CC0_Msk (_UINT32_(0x1) << TC_SYNCBUSY_CC0_Pos) /* (TC_SYNCBUSY) Compare Channel 0 Mask */ 372 #define TC_SYNCBUSY_CC0(value) (TC_SYNCBUSY_CC0_Msk & (_UINT32_(value) << TC_SYNCBUSY_CC0_Pos)) /* Assigment of value for CC0 in the TC_SYNCBUSY register */ 373 #define TC_SYNCBUSY_CC1_Pos _UINT32_(7) /* (TC_SYNCBUSY) Compare Channel 1 Position */ 374 #define TC_SYNCBUSY_CC1_Msk (_UINT32_(0x1) << TC_SYNCBUSY_CC1_Pos) /* (TC_SYNCBUSY) Compare Channel 1 Mask */ 375 #define TC_SYNCBUSY_CC1(value) (TC_SYNCBUSY_CC1_Msk & (_UINT32_(value) << TC_SYNCBUSY_CC1_Pos)) /* Assigment of value for CC1 in the TC_SYNCBUSY register */ 376 #define TC_SYNCBUSY_Msk _UINT32_(0x000000FF) /* (TC_SYNCBUSY) Register Mask */ 377 378 #define TC_SYNCBUSY_CC_Pos _UINT32_(6) /* (TC_SYNCBUSY Position) Compare Channel x */ 379 #define TC_SYNCBUSY_CC_Msk (_UINT32_(0x3) << TC_SYNCBUSY_CC_Pos) /* (TC_SYNCBUSY Mask) CC */ 380 #define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & (_UINT32_(value) << TC_SYNCBUSY_CC_Pos)) 381 382 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 Count -------- */ 383 #define TC_COUNT8_COUNT_RESETVALUE _UINT8_(0x00) /* (TC_COUNT8_COUNT) COUNT8 Count Reset Value */ 384 385 #define TC_COUNT8_COUNT_COUNT_Pos _UINT8_(0) /* (TC_COUNT8_COUNT) Counter Value Position */ 386 #define TC_COUNT8_COUNT_COUNT_Msk (_UINT8_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos) /* (TC_COUNT8_COUNT) Counter Value Mask */ 387 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & (_UINT8_(value) << TC_COUNT8_COUNT_COUNT_Pos)) /* Assigment of value for COUNT in the TC_COUNT8_COUNT register */ 388 #define TC_COUNT8_COUNT_Msk _UINT8_(0xFF) /* (TC_COUNT8_COUNT) Register Mask */ 389 390 391 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 Count -------- */ 392 #define TC_COUNT16_COUNT_RESETVALUE _UINT16_(0x00) /* (TC_COUNT16_COUNT) COUNT16 Count Reset Value */ 393 394 #define TC_COUNT16_COUNT_COUNT_Pos _UINT16_(0) /* (TC_COUNT16_COUNT) Counter Value Position */ 395 #define TC_COUNT16_COUNT_COUNT_Msk (_UINT16_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos) /* (TC_COUNT16_COUNT) Counter Value Mask */ 396 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & (_UINT16_(value) << TC_COUNT16_COUNT_COUNT_Pos)) /* Assigment of value for COUNT in the TC_COUNT16_COUNT register */ 397 #define TC_COUNT16_COUNT_Msk _UINT16_(0xFFFF) /* (TC_COUNT16_COUNT) Register Mask */ 398 399 400 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 Count -------- */ 401 #define TC_COUNT32_COUNT_RESETVALUE _UINT32_(0x00) /* (TC_COUNT32_COUNT) COUNT32 Count Reset Value */ 402 403 #define TC_COUNT32_COUNT_COUNT_Pos _UINT32_(0) /* (TC_COUNT32_COUNT) Counter Value Position */ 404 #define TC_COUNT32_COUNT_COUNT_Msk (_UINT32_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos) /* (TC_COUNT32_COUNT) Counter Value Mask */ 405 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & (_UINT32_(value) << TC_COUNT32_COUNT_COUNT_Pos)) /* Assigment of value for COUNT in the TC_COUNT32_COUNT register */ 406 #define TC_COUNT32_COUNT_Msk _UINT32_(0xFFFFFFFF) /* (TC_COUNT32_COUNT) Register Mask */ 407 408 409 /* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 Period -------- */ 410 #define TC_COUNT8_PER_RESETVALUE _UINT8_(0xFF) /* (TC_COUNT8_PER) COUNT8 Period Reset Value */ 411 412 #define TC_COUNT8_PER_PER_Pos _UINT8_(0) /* (TC_COUNT8_PER) Period Value Position */ 413 #define TC_COUNT8_PER_PER_Msk (_UINT8_(0xFF) << TC_COUNT8_PER_PER_Pos) /* (TC_COUNT8_PER) Period Value Mask */ 414 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & (_UINT8_(value) << TC_COUNT8_PER_PER_Pos)) /* Assigment of value for PER in the TC_COUNT8_PER register */ 415 #define TC_COUNT8_PER_Msk _UINT8_(0xFF) /* (TC_COUNT8_PER) Register Mask */ 416 417 418 /* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 Compare and Capture -------- */ 419 #define TC_COUNT8_CC_RESETVALUE _UINT8_(0x00) /* (TC_COUNT8_CC) COUNT8 Compare and Capture Reset Value */ 420 421 #define TC_COUNT8_CC_CC_Pos _UINT8_(0) /* (TC_COUNT8_CC) Counter/Compare Value Position */ 422 #define TC_COUNT8_CC_CC_Msk (_UINT8_(0xFF) << TC_COUNT8_CC_CC_Pos) /* (TC_COUNT8_CC) Counter/Compare Value Mask */ 423 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & (_UINT8_(value) << TC_COUNT8_CC_CC_Pos)) /* Assigment of value for CC in the TC_COUNT8_CC register */ 424 #define TC_COUNT8_CC_Msk _UINT8_(0xFF) /* (TC_COUNT8_CC) Register Mask */ 425 426 427 /* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 Compare and Capture -------- */ 428 #define TC_COUNT16_CC_RESETVALUE _UINT16_(0x00) /* (TC_COUNT16_CC) COUNT16 Compare and Capture Reset Value */ 429 430 #define TC_COUNT16_CC_CC_Pos _UINT16_(0) /* (TC_COUNT16_CC) Counter/Compare Value Position */ 431 #define TC_COUNT16_CC_CC_Msk (_UINT16_(0xFFFF) << TC_COUNT16_CC_CC_Pos) /* (TC_COUNT16_CC) Counter/Compare Value Mask */ 432 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & (_UINT16_(value) << TC_COUNT16_CC_CC_Pos)) /* Assigment of value for CC in the TC_COUNT16_CC register */ 433 #define TC_COUNT16_CC_Msk _UINT16_(0xFFFF) /* (TC_COUNT16_CC) Register Mask */ 434 435 436 /* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 Compare and Capture -------- */ 437 #define TC_COUNT32_CC_RESETVALUE _UINT32_(0x00) /* (TC_COUNT32_CC) COUNT32 Compare and Capture Reset Value */ 438 439 #define TC_COUNT32_CC_CC_Pos _UINT32_(0) /* (TC_COUNT32_CC) Counter/Compare Value Position */ 440 #define TC_COUNT32_CC_CC_Msk (_UINT32_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos) /* (TC_COUNT32_CC) Counter/Compare Value Mask */ 441 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & (_UINT32_(value) << TC_COUNT32_CC_CC_Pos)) /* Assigment of value for CC in the TC_COUNT32_CC register */ 442 #define TC_COUNT32_CC_Msk _UINT32_(0xFFFFFFFF) /* (TC_COUNT32_CC) Register Mask */ 443 444 445 /* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 Period Buffer -------- */ 446 #define TC_COUNT8_PERBUF_RESETVALUE _UINT8_(0xFF) /* (TC_COUNT8_PERBUF) COUNT8 Period Buffer Reset Value */ 447 448 #define TC_COUNT8_PERBUF_PERBUF_Pos _UINT8_(0) /* (TC_COUNT8_PERBUF) Period Buffer Value Position */ 449 #define TC_COUNT8_PERBUF_PERBUF_Msk (_UINT8_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos) /* (TC_COUNT8_PERBUF) Period Buffer Value Mask */ 450 #define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & (_UINT8_(value) << TC_COUNT8_PERBUF_PERBUF_Pos)) /* Assigment of value for PERBUF in the TC_COUNT8_PERBUF register */ 451 #define TC_COUNT8_PERBUF_Msk _UINT8_(0xFF) /* (TC_COUNT8_PERBUF) Register Mask */ 452 453 454 /* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 Compare and Capture Buffer -------- */ 455 #define TC_COUNT8_CCBUF_RESETVALUE _UINT8_(0x00) /* (TC_COUNT8_CCBUF) COUNT8 Compare and Capture Buffer Reset Value */ 456 457 #define TC_COUNT8_CCBUF_CCBUF_Pos _UINT8_(0) /* (TC_COUNT8_CCBUF) Counter/Compare Buffer Value Position */ 458 #define TC_COUNT8_CCBUF_CCBUF_Msk (_UINT8_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos) /* (TC_COUNT8_CCBUF) Counter/Compare Buffer Value Mask */ 459 #define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & (_UINT8_(value) << TC_COUNT8_CCBUF_CCBUF_Pos)) /* Assigment of value for CCBUF in the TC_COUNT8_CCBUF register */ 460 #define TC_COUNT8_CCBUF_Msk _UINT8_(0xFF) /* (TC_COUNT8_CCBUF) Register Mask */ 461 462 463 /* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 Compare and Capture Buffer -------- */ 464 #define TC_COUNT16_CCBUF_RESETVALUE _UINT16_(0x00) /* (TC_COUNT16_CCBUF) COUNT16 Compare and Capture Buffer Reset Value */ 465 466 #define TC_COUNT16_CCBUF_CCBUF_Pos _UINT16_(0) /* (TC_COUNT16_CCBUF) Counter/Compare Buffer Value Position */ 467 #define TC_COUNT16_CCBUF_CCBUF_Msk (_UINT16_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos) /* (TC_COUNT16_CCBUF) Counter/Compare Buffer Value Mask */ 468 #define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & (_UINT16_(value) << TC_COUNT16_CCBUF_CCBUF_Pos)) /* Assigment of value for CCBUF in the TC_COUNT16_CCBUF register */ 469 #define TC_COUNT16_CCBUF_Msk _UINT16_(0xFFFF) /* (TC_COUNT16_CCBUF) Register Mask */ 470 471 472 /* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 Compare and Capture Buffer -------- */ 473 #define TC_COUNT32_CCBUF_RESETVALUE _UINT32_(0x00) /* (TC_COUNT32_CCBUF) COUNT32 Compare and Capture Buffer Reset Value */ 474 475 #define TC_COUNT32_CCBUF_CCBUF_Pos _UINT32_(0) /* (TC_COUNT32_CCBUF) Counter/Compare Buffer Value Position */ 476 #define TC_COUNT32_CCBUF_CCBUF_Msk (_UINT32_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos) /* (TC_COUNT32_CCBUF) Counter/Compare Buffer Value Mask */ 477 #define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & (_UINT32_(value) << TC_COUNT32_CCBUF_CCBUF_Pos)) /* Assigment of value for CCBUF in the TC_COUNT32_CCBUF register */ 478 #define TC_COUNT32_CCBUF_Msk _UINT32_(0xFFFFFFFF) /* (TC_COUNT32_CCBUF) Register Mask */ 479 480 481 /** \brief TC register offsets definitions */ 482 #define TC_CTRLA_REG_OFST _UINT32_(0x00) /* (TC_CTRLA) Control A Offset */ 483 #define TC_CTRLBCLR_REG_OFST _UINT32_(0x04) /* (TC_CTRLBCLR) Control B Clear Offset */ 484 #define TC_CTRLBSET_REG_OFST _UINT32_(0x05) /* (TC_CTRLBSET) Control B Set Offset */ 485 #define TC_EVCTRL_REG_OFST _UINT32_(0x06) /* (TC_EVCTRL) Event Control Offset */ 486 #define TC_INTENCLR_REG_OFST _UINT32_(0x08) /* (TC_INTENCLR) Interrupt Enable Clear Offset */ 487 #define TC_INTENSET_REG_OFST _UINT32_(0x09) /* (TC_INTENSET) Interrupt Enable Set Offset */ 488 #define TC_INTFLAG_REG_OFST _UINT32_(0x0A) /* (TC_INTFLAG) Interrupt Flag Status and Clear Offset */ 489 #define TC_STATUS_REG_OFST _UINT32_(0x0B) /* (TC_STATUS) Status Offset */ 490 #define TC_WAVE_REG_OFST _UINT32_(0x0C) /* (TC_WAVE) Waveform Generation Control Offset */ 491 #define TC_DRVCTRL_REG_OFST _UINT32_(0x0D) /* (TC_DRVCTRL) Control C Offset */ 492 #define TC_DBGCTRL_REG_OFST _UINT32_(0x0F) /* (TC_DBGCTRL) Debug Control Offset */ 493 #define TC_SYNCBUSY_REG_OFST _UINT32_(0x10) /* (TC_SYNCBUSY) Synchronization Status Offset */ 494 #define TC_COUNT8_COUNT_REG_OFST _UINT32_(0x14) /* (TC_COUNT8_COUNT) COUNT8 Count Offset */ 495 #define TC_COUNT16_COUNT_REG_OFST _UINT32_(0x14) /* (TC_COUNT16_COUNT) COUNT16 Count Offset */ 496 #define TC_COUNT32_COUNT_REG_OFST _UINT32_(0x14) /* (TC_COUNT32_COUNT) COUNT32 Count Offset */ 497 #define TC_COUNT8_PER_REG_OFST _UINT32_(0x1B) /* (TC_COUNT8_PER) COUNT8 Period Offset */ 498 #define TC_COUNT8_CC_REG_OFST _UINT32_(0x1C) /* (TC_COUNT8_CC) COUNT8 Compare and Capture Offset */ 499 #define TC_COUNT8_CC0_REG_OFST _UINT32_(0x1C) /* (TC_COUNT8_CC0) COUNT8 Compare and Capture Offset */ 500 #define TC_COUNT8_CC1_REG_OFST _UINT32_(0x1D) /* (TC_COUNT8_CC1) COUNT8 Compare and Capture Offset */ 501 #define TC_COUNT16_CC_REG_OFST _UINT32_(0x1C) /* (TC_COUNT16_CC) COUNT16 Compare and Capture Offset */ 502 #define TC_COUNT16_CC0_REG_OFST _UINT32_(0x1C) /* (TC_COUNT16_CC0) COUNT16 Compare and Capture Offset */ 503 #define TC_COUNT16_CC1_REG_OFST _UINT32_(0x1E) /* (TC_COUNT16_CC1) COUNT16 Compare and Capture Offset */ 504 #define TC_COUNT32_CC_REG_OFST _UINT32_(0x1C) /* (TC_COUNT32_CC) COUNT32 Compare and Capture Offset */ 505 #define TC_COUNT32_CC0_REG_OFST _UINT32_(0x1C) /* (TC_COUNT32_CC0) COUNT32 Compare and Capture Offset */ 506 #define TC_COUNT32_CC1_REG_OFST _UINT32_(0x20) /* (TC_COUNT32_CC1) COUNT32 Compare and Capture Offset */ 507 #define TC_COUNT8_PERBUF_REG_OFST _UINT32_(0x2F) /* (TC_COUNT8_PERBUF) COUNT8 Period Buffer Offset */ 508 #define TC_COUNT8_CCBUF_REG_OFST _UINT32_(0x30) /* (TC_COUNT8_CCBUF) COUNT8 Compare and Capture Buffer Offset */ 509 #define TC_COUNT8_CCBUF0_REG_OFST _UINT32_(0x30) /* (TC_COUNT8_CCBUF0) COUNT8 Compare and Capture Buffer Offset */ 510 #define TC_COUNT8_CCBUF1_REG_OFST _UINT32_(0x31) /* (TC_COUNT8_CCBUF1) COUNT8 Compare and Capture Buffer Offset */ 511 #define TC_COUNT16_CCBUF_REG_OFST _UINT32_(0x30) /* (TC_COUNT16_CCBUF) COUNT16 Compare and Capture Buffer Offset */ 512 #define TC_COUNT16_CCBUF0_REG_OFST _UINT32_(0x30) /* (TC_COUNT16_CCBUF0) COUNT16 Compare and Capture Buffer Offset */ 513 #define TC_COUNT16_CCBUF1_REG_OFST _UINT32_(0x32) /* (TC_COUNT16_CCBUF1) COUNT16 Compare and Capture Buffer Offset */ 514 #define TC_COUNT32_CCBUF_REG_OFST _UINT32_(0x30) /* (TC_COUNT32_CCBUF) COUNT32 Compare and Capture Buffer Offset */ 515 #define TC_COUNT32_CCBUF0_REG_OFST _UINT32_(0x30) /* (TC_COUNT32_CCBUF0) COUNT32 Compare and Capture Buffer Offset */ 516 #define TC_COUNT32_CCBUF1_REG_OFST _UINT32_(0x34) /* (TC_COUNT32_CCBUF1) COUNT32 Compare and Capture Buffer Offset */ 517 518 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 519 /** \brief TC register API structure */ 520 typedef struct 521 { /* Basic Timer Counter */ 522 __IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ 523 __IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */ 524 __IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */ 525 __IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */ 526 __IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 527 __IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */ 528 __IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 529 __IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */ 530 __IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Generation Control */ 531 __IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */ 532 __I uint8_t Reserved1[0x01]; 533 __IO uint8_t TC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */ 534 __I uint32_t TC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */ 535 __IO uint8_t TC_COUNT; /**< Offset: 0x14 (R/W 8) COUNT8 Count */ 536 __I uint8_t Reserved2[0x06]; 537 __IO uint8_t TC_PER; /**< Offset: 0x1B (R/W 8) COUNT8 Period */ 538 __IO uint8_t TC_CC[2]; /**< Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */ 539 __I uint8_t Reserved3[0x11]; 540 __IO uint8_t TC_PERBUF; /**< Offset: 0x2F (R/W 8) COUNT8 Period Buffer */ 541 __IO uint8_t TC_CCBUF[2]; /**< Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */ 542 } tc_count8_registers_t; 543 544 /** \brief TC register API structure */ 545 typedef struct 546 { /* Basic Timer Counter */ 547 __IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ 548 __IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */ 549 __IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */ 550 __IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */ 551 __IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 552 __IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */ 553 __IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 554 __IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */ 555 __IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Generation Control */ 556 __IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */ 557 __I uint8_t Reserved1[0x01]; 558 __IO uint8_t TC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */ 559 __I uint32_t TC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */ 560 __IO uint16_t TC_COUNT; /**< Offset: 0x14 (R/W 16) COUNT16 Count */ 561 __I uint8_t Reserved2[0x06]; 562 __IO uint16_t TC_CC[2]; /**< Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */ 563 __I uint8_t Reserved3[0x10]; 564 __IO uint16_t TC_CCBUF[2]; /**< Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */ 565 } tc_count16_registers_t; 566 567 /** \brief TC register API structure */ 568 typedef struct 569 { /* Basic Timer Counter */ 570 __IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ 571 __IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */ 572 __IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */ 573 __IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */ 574 __IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 575 __IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */ 576 __IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 577 __IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */ 578 __IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Generation Control */ 579 __IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */ 580 __I uint8_t Reserved1[0x01]; 581 __IO uint8_t TC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */ 582 __I uint32_t TC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */ 583 __IO uint32_t TC_COUNT; /**< Offset: 0x14 (R/W 32) COUNT32 Count */ 584 __I uint8_t Reserved2[0x04]; 585 __IO uint32_t TC_CC[2]; /**< Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */ 586 __I uint8_t Reserved3[0x0C]; 587 __IO uint32_t TC_CCBUF[2]; /**< Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */ 588 } tc_count32_registers_t; 589 590 /** \brief TC hardware registers */ 591 typedef union 592 { /* Basic Timer Counter */ 593 tc_count8_registers_t COUNT8; /**< 8-bit Counter Mode */ 594 tc_count16_registers_t COUNT16; /**< 16-bit Counter Mode */ 595 tc_count32_registers_t COUNT32; /**< 32-bit Counter Mode */ 596 } tc_registers_t; 597 598 599 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 600 #endif /* _PIC32CXSG60_TC_COMPONENT_H_ */ 601
