1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TC_COMPONENT_FIXUP_H_ 9 10 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */ 17 uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */ 18 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 19 uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */ 20 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 21 uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */ 22 uint32_t :4; /*!< bit: 12..15 Reserved */ 23 uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */ 24 uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */ 25 uint32_t :2; /*!< bit: 18..19 Reserved */ 26 uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */ 27 uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */ 28 uint32_t :2; /*!< bit: 22..23 Reserved */ 29 uint32_t CAPTMODE0:2; /*!< bit: 24..25 Capture Mode Channel 0 */ 30 uint32_t :1; /*!< bit: 26 Reserved */ 31 uint32_t CAPTMODE1:2; /*!< bit: 27..28 Capture mode Channel 1 */ 32 uint32_t :3; /*!< bit: 29..31 Reserved */ 33 } bit; /*!< Structure used for bit access */ 34 struct { 35 uint32_t :16; /*!< bit: 0..15 Reserved */ 36 uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */ 37 uint32_t :2; /*!< bit: 18..19 Reserved */ 38 uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */ 39 uint32_t :10; /*!< bit: 22..31 Reserved */ 40 } vec; /*!< Structure used for vec access */ 41 uint32_t reg; /*!< Type used for register access */ 42 } TC_CTRLA_Type; 43 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 44 45 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 typedef union { 48 struct { 49 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 50 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 51 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ 52 uint8_t :2; /*!< bit: 3.. 4 Reserved */ 53 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 54 } bit; /*!< Structure used for bit access */ 55 uint8_t reg; /*!< Type used for register access */ 56 } TC_CTRLBCLR_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 64 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 65 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ 66 uint8_t :2; /*!< bit: 3.. 4 Reserved */ 67 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 68 } bit; /*!< Structure used for bit access */ 69 uint8_t reg; /*!< Type used for register access */ 70 } TC_CTRLBSET_Type; 71 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 /* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */ 74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 75 typedef union { 76 struct { 77 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ 78 uint16_t :1; /*!< bit: 3 Reserved */ 79 uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */ 80 uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */ 81 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 82 uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */ 83 uint16_t :3; /*!< bit: 9..11 Reserved */ 84 uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */ 85 uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */ 86 uint16_t :2; /*!< bit: 14..15 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 struct { 89 uint16_t :12; /*!< bit: 0..11 Reserved */ 90 uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */ 91 uint16_t :2; /*!< bit: 14..15 Reserved */ 92 } vec; /*!< Structure used for vec access */ 93 uint16_t reg; /*!< Type used for register access */ 94 } TC_EVCTRL_Type; 95 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 96 97 /* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 struct { 101 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */ 102 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */ 103 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 104 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */ 105 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */ 106 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 107 } bit; /*!< Structure used for bit access */ 108 struct { 109 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 110 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */ 111 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 112 } vec; /*!< Structure used for vec access */ 113 uint8_t reg; /*!< Type used for register access */ 114 } TC_INTENCLR_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 /* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 119 typedef union { 120 struct { 121 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */ 122 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */ 123 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 124 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */ 125 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */ 126 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 127 } bit; /*!< Structure used for bit access */ 128 struct { 129 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 130 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */ 131 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 132 } vec; /*!< Structure used for vec access */ 133 uint8_t reg; /*!< Type used for register access */ 134 } TC_INTENSET_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { // __I to avoid read-modify-write on write-to-clear register 140 struct { 141 __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */ 142 __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */ 143 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 144 __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */ 145 __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */ 146 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 147 } bit; /*!< Structure used for bit access */ 148 struct { 149 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ 150 __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */ 151 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 152 } vec; /*!< Structure used for vec access */ 153 uint8_t reg; /*!< Type used for register access */ 154 } TC_INTFLAG_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 /* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */ 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 159 typedef union { 160 struct { 161 uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */ 162 uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */ 163 uint8_t :1; /*!< bit: 2 Reserved */ 164 uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */ 165 uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */ 166 uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */ 167 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 168 } bit; /*!< Structure used for bit access */ 169 struct { 170 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 171 uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */ 172 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 173 } vec; /*!< Structure used for vec access */ 174 uint8_t reg; /*!< Type used for register access */ 175 } TC_STATUS_Type; 176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 /* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */ 183 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 184 } bit; /*!< Structure used for bit access */ 185 uint8_t reg; /*!< Type used for register access */ 186 } TC_WAVE_Type; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 /* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */ 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 191 typedef union { 192 struct { 193 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */ 194 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */ 195 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 196 } bit; /*!< Structure used for bit access */ 197 struct { 198 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */ 199 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 200 } vec; /*!< Structure used for vec access */ 201 uint8_t reg; /*!< Type used for register access */ 202 } TC_DRVCTRL_Type; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 /* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */ 206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 207 typedef union { 208 struct { 209 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 210 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 211 } bit; /*!< Structure used for bit access */ 212 uint8_t reg; /*!< Type used for register access */ 213 } TC_DBGCTRL_Type; 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 215 216 /* -------- TC_SYNCBUSY : (TC Offset: 0x10) ( R/ 32) Synchronization Status -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint32_t SWRST:1; /*!< bit: 0 swrst */ 221 uint32_t ENABLE:1; /*!< bit: 1 enable */ 222 uint32_t CTRLB:1; /*!< bit: 2 CTRLB */ 223 uint32_t STATUS:1; /*!< bit: 3 STATUS */ 224 uint32_t COUNT:1; /*!< bit: 4 Counter */ 225 uint32_t PER:1; /*!< bit: 5 Period */ 226 uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */ 227 uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */ 228 uint32_t :24; /*!< bit: 8..31 Reserved */ 229 } bit; /*!< Structure used for bit access */ 230 struct { 231 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 232 uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */ 233 uint32_t :24; /*!< bit: 8..31 Reserved */ 234 } vec; /*!< Structure used for vec access */ 235 uint32_t reg; /*!< Type used for register access */ 236 } TC_SYNCBUSY_Type; 237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 238 239 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 Count -------- */ 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 241 typedef union { 242 struct { 243 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ 244 } bit; /*!< Structure used for bit access */ 245 uint8_t reg; /*!< Type used for register access */ 246 } TC_COUNT8_COUNT_Type; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 Count -------- */ 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 251 typedef union { 252 struct { 253 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 254 } bit; /*!< Structure used for bit access */ 255 uint16_t reg; /*!< Type used for register access */ 256 } TC_COUNT16_COUNT_Type; 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 259 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 Count -------- */ 260 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 261 typedef union { 262 struct { 263 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 264 } bit; /*!< Structure used for bit access */ 265 uint32_t reg; /*!< Type used for register access */ 266 } TC_COUNT32_COUNT_Type; 267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 268 269 /* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 Period -------- */ 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 271 typedef union { 272 struct { 273 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ 274 } bit; /*!< Structure used for bit access */ 275 uint8_t reg; /*!< Type used for register access */ 276 } TC_COUNT8_PER_Type; 277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 278 279 /* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 Compare and Capture -------- */ 280 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 281 typedef union { 282 struct { 283 uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */ 284 } bit; /*!< Structure used for bit access */ 285 uint8_t reg; /*!< Type used for register access */ 286 } TC_COUNT8_CC_Type; 287 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 288 289 /* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 Compare and Capture -------- */ 290 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 291 typedef union { 292 struct { 293 uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */ 294 } bit; /*!< Structure used for bit access */ 295 uint16_t reg; /*!< Type used for register access */ 296 } TC_COUNT16_CC_Type; 297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 298 299 /* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 Compare and Capture -------- */ 300 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 301 typedef union { 302 struct { 303 uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */ 304 } bit; /*!< Structure used for bit access */ 305 uint32_t reg; /*!< Type used for register access */ 306 } TC_COUNT32_CC_Type; 307 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 308 309 /* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 Period Buffer -------- */ 310 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 311 typedef union { 312 struct { 313 uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */ 314 } bit; /*!< Structure used for bit access */ 315 uint8_t reg; /*!< Type used for register access */ 316 } TC_COUNT8_PERBUF_Type; 317 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 318 319 /* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 Compare and Capture Buffer -------- */ 320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 321 typedef union { 322 struct { 323 uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */ 324 } bit; /*!< Structure used for bit access */ 325 uint8_t reg; /*!< Type used for register access */ 326 } TC_COUNT8_CCBUF_Type; 327 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 328 329 /* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 Compare and Capture Buffer -------- */ 330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 331 typedef union { 332 struct { 333 uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */ 334 } bit; /*!< Structure used for bit access */ 335 uint16_t reg; /*!< Type used for register access */ 336 } TC_COUNT16_CCBUF_Type; 337 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 338 339 /* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 Compare and Capture Buffer -------- */ 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 341 typedef union { 342 struct { 343 uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */ 344 } bit; /*!< Structure used for bit access */ 345 uint32_t reg; /*!< Type used for register access */ 346 } TC_COUNT32_CCBUF_Type; 347 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 348 349 /** \brief TC_COUNT8 hardware registers */ 350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 351 typedef struct { /* 8-bit Counter Mode */ 352 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 353 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 354 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 355 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 356 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 357 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 358 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 359 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 360 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 361 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 362 RoReg8 Reserved1[0x1]; 363 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 364 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 365 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */ 366 RoReg8 Reserved2[0x6]; 367 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */ 368 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */ 369 RoReg8 Reserved3[0x11]; 370 __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */ 371 __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */ 372 } TcCount8; 373 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 374 375 /** \brief TC_COUNT16 hardware registers */ 376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 377 typedef struct { /* 16-bit Counter Mode */ 378 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 379 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 380 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 381 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 382 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 383 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 384 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 385 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 386 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 387 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 388 RoReg8 Reserved1[0x1]; 389 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 390 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 391 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */ 392 RoReg8 Reserved2[0x6]; 393 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */ 394 RoReg8 Reserved3[0x10]; 395 __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */ 396 } TcCount16; 397 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 398 399 /** \brief TC_COUNT32 hardware registers */ 400 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 401 typedef struct { /* 32-bit Counter Mode */ 402 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 403 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 404 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 405 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 406 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 407 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 408 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 409 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 410 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 411 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 412 RoReg8 Reserved1[0x1]; 413 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 414 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 415 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */ 416 RoReg8 Reserved2[0x4]; 417 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */ 418 RoReg8 Reserved3[0xC]; 419 __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */ 420 } TcCount32; 421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 422 423 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 424 typedef union { 425 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ 426 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ 427 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ 428 } Tc; 429 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 430 431 432 433 434 435 436 #endif /* _MICROCHIP_PIC32CXSG_TC_COMPONENT_FIXUP_H_ */ 437
