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Searched refs:STM32_DOMAIN_CLOCK (Results 1 – 22 of 22) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h5_clock.h76 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
97 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR1_REG)
98 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR1_REG)
99 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR1_REG)
100 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR1_REG)
101 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR1_REG)
102 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR1_REG)
103 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 18, CCIPR1_REG)
104 #define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, CCIPR1_REG)
105 #define USART9_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR1_REG)
[all …]
Dstm32u5_clock.h77 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
96 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
97 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
98 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG)
99 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG)
100 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG)
101 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
102 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG)
103 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG)
104 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG)
[all …]
Dstm32l4_clock.h62 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
81 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
82 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
83 #define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
84 #define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
85 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
86 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
87 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
88 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
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Dstm32h7_clock.h83 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
103 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
104 #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
105 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)
106 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
109 #define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
111 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)
112 #define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)
113 #define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)
[all …]
Dstm32g0_clock.h60 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
77 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
78 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG)
79 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
82 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
83 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
[all …]
Dstm32g4_clock.h64 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
79 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
80 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
81 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
82 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
83 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
84 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
85 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
86 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
87 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
[all …]
Dstm32f7_clock.h66 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
80 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
94 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
102 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)
103 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)
104 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)
105 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)
106 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)
107 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)
108 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)
[all …]
Dstm32f3_clock.h56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
71 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
76 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
77 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)
78 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
79 #define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)
80 #define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)
81 #define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)
82 #define TIM16_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)
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Dstm32h7rs_clock.h79 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
102 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
103 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG)
104 #define XSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
105 #define XSPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG)
106 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG)
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
110 #define USART234578_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG)
111 #define SPI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG)
112 #define I2C23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIPR_REG)
[all …]
Dstm32f410_clock.h15 #define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
16 #define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
17 #define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
18 #define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
19 #define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG)
20 #define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG)
21 #define CKDFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG)
24 #define I2CFMP1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
25 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
26 #define SDIO_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
[all …]
Dstm32u0_clock.h61 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
77 #define LPUART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
78 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
79 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
80 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
81 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
82 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
83 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
[all …]
Dstm32wl_clock.h63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
77 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
78 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
79 #define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
82 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
[all …]
Dstm32wba_clock.h71 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
86 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
87 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
88 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
89 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)
90 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)
91 #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)
92 #define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG)
94 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
96 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR3_REG)
[all …]
Dstm32wb_clock.h63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
81 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
82 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
86 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
[all …]
Dstm32f427_clock.h14 #define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
15 #define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
16 #define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
17 #define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
18 #define CLK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG)
19 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG)
20 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG)
Dstm32l0_clock.h56 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
71 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
72 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
73 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
74 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
75 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
76 #define HSI48_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, CCIPR_REG)
78 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG)
Dstm32f0_clock.h55 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
70 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
71 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
72 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
73 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG)
74 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
75 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
77 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
Dstm32c0_clock.h54 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
71 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
72 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
73 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
74 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
76 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)
Dstm32wb0_clock.h52 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
65 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */
66 #define SPI2_I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG) /* WB06/WB07 only */
68 #define SPI3_I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG)
Dstm32f1_clock.h53 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
68 #define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG)
69 #define I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG)
71 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
Dstm32f4_clock.h68 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
81 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
87 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
Dstm32l1_clock.h51 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
60 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG)