Lines Matching refs:STM32_DOMAIN_CLOCK
83 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
103 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
104 #define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
105 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)
106 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)
107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
109 #define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
111 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)
112 #define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)
113 #define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)
114 #define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG)
115 #define SPDIF_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG)
116 #define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG)
117 #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG)
118 #define SWP_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG)
120 #define USART2345678_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG)
121 #define USART16_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG)
122 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG)
123 #define I2C123_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG)
124 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG)
125 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG)
126 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG)
128 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
129 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)
130 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)
131 #define LPTIM345_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)
132 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)
133 #define SAI4A_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)
134 #define SAI4B_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)
135 #define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)
137 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)