1 /* 2 * Copyright (c) 2022 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Domain clocks */ 12 13 /** Bus clocks */ 14 #define STM32_CLOCK_BUS_AHB1 0x030 15 #define STM32_CLOCK_BUS_AHB2 0x034 16 #define STM32_CLOCK_BUS_AHB3 0x038 17 #define STM32_CLOCK_BUS_APB1 0x040 18 #define STM32_CLOCK_BUS_APB2 0x044 19 #define STM32_CLOCK_BUS_APB3 0x0A8 20 21 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 22 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 23 24 /** Domain clocks */ 25 /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */ 26 27 /** System clock */ 28 /* defined in stm32_common_clocks.h */ 29 30 /** Fixed clocks */ 31 /* Low speed clocks defined in stm32_common_clocks.h */ 32 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 33 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) 34 /** PLL clock outputs */ 35 #define STM32_SRC_PLL_P (STM32_SRC_HSE + 1) 36 #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) 37 #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) 38 /** Peripheral bus clock */ 39 #define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1) 40 41 #define STM32_SRC_PLLI2S_R (STM32_SRC_PCLK + 1) 42 43 44 #define STM32_CLOCK_REG_MASK 0xFFU 45 #define STM32_CLOCK_REG_SHIFT 0U 46 #define STM32_CLOCK_SHIFT_MASK 0x1FU 47 #define STM32_CLOCK_SHIFT_SHIFT 8U 48 #define STM32_CLOCK_MASK_MASK 0x7U 49 #define STM32_CLOCK_MASK_SHIFT 13U 50 #define STM32_CLOCK_VAL_MASK 0x7U 51 #define STM32_CLOCK_VAL_SHIFT 16U 52 53 /** 54 * @brief STM32 clock configuration bit field. 55 * 56 * - reg (1/2/3) [ 0 : 7 ] 57 * - shift (0..31) [ 8 : 12 ] 58 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 59 * - val (0..7) [ 16 : 18 ] 60 * 61 * @param reg RCC_CFGRx register offset 62 * @param shift Position within RCC_CFGRx. 63 * @param mask Mask for the RCC_CFGRx field. 64 * @param val Clock value (0, 1, ... 7). 65 */ 66 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 67 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 68 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 69 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 70 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 71 72 /** @brief RCC_CFGRx register offset */ 73 #define CFGR_REG 0x08 74 75 /** @brief RCC_BDCR register offset */ 76 #define BDCR_REG 0x70 77 78 /** @brief Device domain clocks selection helpers */ 79 /** CFGR devices */ 80 #define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) 81 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) 82 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) 83 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) 84 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) 85 86 /* MCO prescaler : division factor */ 87 #define MCO_PRE_DIV_1 0 88 #define MCO_PRE_DIV_2 4 89 #define MCO_PRE_DIV_3 5 90 #define MCO_PRE_DIV_4 6 91 #define MCO_PRE_DIV_5 7 92 93 /** BDCR devices */ 94 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) 95 96 /** @brief RCC_DKCFGR register offset */ 97 #define DCKCFGR1_REG 0x8C 98 #define DCKCFGR2_REG 0x90 99 100 /** @brief Dedicated clocks configuration register selection helpers */ 101 /** DKCFGR2 devices */ 102 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG) 103 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG) 104 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG) 105 #define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG) 106 #define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG) 107 #define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG) 108 #define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG) 109 #define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG) 110 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG) 111 #define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG) 112 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG) 113 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG) 114 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG) 115 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG) 116 #define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) 117 #define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG) 118 #define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG) 119 #define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG) 120 121 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */ 122
