Lines Matching refs:STM32_DOMAIN_CLOCK
63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
80 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
81 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
82 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
83 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
84 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
85 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
86 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
89 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
91 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
93 #define RFWKP_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG)