1 /* 2 * Copyright (c) 2022 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Domain clocks */ 12 13 /** Bus clocks */ 14 #define STM32_CLOCK_BUS_AHB1 0x014 15 #define STM32_CLOCK_BUS_APB2 0x018 16 #define STM32_CLOCK_BUS_APB1 0x01c 17 18 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 19 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 20 21 /** System clock */ 22 /* defined in stm32_common_clocks.h */ 23 24 /** Fixed clocks */ 25 /* Low speed clocks defined in stm32_common_clocks.h */ 26 #define STM32_SRC_HSI (STM32_SRC_LSI + 1) 27 #define STM32_SRC_HSE (STM32_SRC_HSI + 1) 28 #define STM32_SRC_EXT_HSE (STM32_SRC_HSE + 1) 29 #define STM32_SRC_PLLCLK (STM32_SRC_EXT_HSE + 1) 30 31 #define STM32_CLOCK_REG_MASK 0xFFU 32 #define STM32_CLOCK_REG_SHIFT 0U 33 #define STM32_CLOCK_SHIFT_MASK 0x1FU 34 #define STM32_CLOCK_SHIFT_SHIFT 8U 35 #define STM32_CLOCK_MASK_MASK 0x7U 36 #define STM32_CLOCK_MASK_SHIFT 13U 37 #define STM32_CLOCK_VAL_MASK 0x7U 38 #define STM32_CLOCK_VAL_SHIFT 16U 39 40 /** 41 * @brief STM32 clock configuration bit field. 42 * 43 * - reg (1/2/3) [ 0 : 7 ] 44 * - shift (0..31) [ 8 : 12 ] 45 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 46 * - val (0..7) [ 16 : 18 ] 47 * 48 * @param reg RCC_CFGRx register offset 49 * @param shift Position within RCC_CFGRx. 50 * @param mask Mask for the RCC_CFGRx field. 51 * @param val Clock value (0, 1, ... 7). 52 */ 53 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 54 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 55 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 56 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 57 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 58 59 /** @brief RCC_CFGRx register offset */ 60 #define CFGR1_REG 0x04 61 #define CFGR2_REG 0x2C 62 63 /** @brief RCC_BDCR register offset */ 64 #define BDCR_REG 0x20 65 66 /** @brief Device domain clocks selection helpers */ 67 /** CFGR2 devices */ 68 #define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG) 69 #define I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG) 70 /** BDCR devices */ 71 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) 72 73 /** CFGR1 devices */ 74 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) 75 /* No MCO prescaler support on STM32F1 series. */ 76 77 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */ 78
