Lines Matching refs:STM32_DOMAIN_CLOCK

79 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\  macro
102 #define FMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
103 #define SDMMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG)
104 #define XSPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
105 #define XSPI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG)
106 #define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG)
107 #define CKPER_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
110 #define USART234578_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG)
111 #define SPI23_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG)
112 #define I2C23_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIPR_REG)
113 #define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG)
114 #define I3C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG)
115 #define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIPR_REG)
116 #define FDCAN_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIPR_REG)
119 #define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
120 #define SPI45_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D3CCIPR_REG)
121 #define SPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 8, D3CCIPR_REG)
122 #define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D3CCIPR_REG)
123 #define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 20, D3CCIPR_REG)
126 #define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D4CCIPR_REG)
127 #define SPI6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D4CCIPR_REG)
128 #define LPTIM23_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 8, D4CCIPR_REG)
129 #define LPTIM45_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 12, D4CCIPR_REG)
132 #define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)