Lines Matching refs:STM32_DOMAIN_CLOCK
60 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ macro
75 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
76 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
77 #define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
78 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG)
79 #define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
81 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
82 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
83 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
84 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
85 #define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CCIPR_REG)
86 #define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG)
87 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
88 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
90 #define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
91 #define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR2_REG)
92 #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR2_REG)
93 #define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
95 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)