1 /* 2 * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Bus clocks */ 12 #define STM32_CLOCK_BUS_IOP 0x034 13 #define STM32_CLOCK_BUS_AHB1 0x038 14 #define STM32_CLOCK_BUS_APB1 0x03c 15 #define STM32_CLOCK_BUS_APB1_2 0x040 16 17 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP 18 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 19 20 /** Domain clocks */ 21 /* RM0490, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */ 22 23 /** System clock */ 24 /* defined in stm32_common_clocks.h */ 25 /** Fixed clocks */ 26 /* Low speed clocks defined in stm32_common_clocks.h */ 27 #define STM32_SRC_HSI48 (STM32_SRC_LSI + 1) 28 #define STM32_SRC_HSE (STM32_SRC_HSI48 + 1) 29 /** Peripheral bus clock */ 30 #define STM32_SRC_PCLK (STM32_SRC_HSE + 1) 31 32 #define STM32_CLOCK_REG_MASK 0xFFU 33 #define STM32_CLOCK_REG_SHIFT 0U 34 #define STM32_CLOCK_SHIFT_MASK 0x1FU 35 #define STM32_CLOCK_SHIFT_SHIFT 8U 36 #define STM32_CLOCK_MASK_MASK 0x7U 37 #define STM32_CLOCK_MASK_SHIFT 13U 38 #define STM32_CLOCK_VAL_MASK 0x7U 39 #define STM32_CLOCK_VAL_SHIFT 16U 40 41 /** 42 * @brief STM32 clock configuration bit field. 43 * 44 * - reg (1/2/3) [ 0 : 7 ] 45 * - shift (0..31) [ 8 : 12 ] 46 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 47 * - val (0..7) [ 16 : 18 ] 48 * 49 * @param reg RCC_CCIPRx register offset 50 * @param shift Position within RCC_CCIPRx. 51 * @param mask Mask for the RCC_CCIPRx field. 52 * @param val Clock value (0, 1, ... 7). 53 */ 54 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 57 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 59 60 /** @brief RCC_CCIPR register offset */ 61 #define CCIPR_REG 0x54 62 63 /** @brief RCC_CSR1 register offset */ 64 #define CSR1_REG 0x5C 65 66 /** @brief RCC_CFGRx register offset */ 67 #define CFGR1_REG 0x08 68 69 /** @brief Device domain clocks selection helpers */ 70 /** CCIPR devices */ 71 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) 72 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) 73 #define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) 74 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) 75 /** CSR1 devices */ 76 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG) 77 78 /** CFGR1 devices */ 79 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) 80 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) 81 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG) 82 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG) 83 84 /* MCO prescaler : division factor */ 85 #define MCO_PRE_DIV_1 0 86 #define MCO_PRE_DIV_2 1 87 #define MCO_PRE_DIV_4 2 88 #define MCO_PRE_DIV_8 3 89 #define MCO_PRE_DIV_16 4 90 #define MCO_PRE_DIV_32 5 91 #define MCO_PRE_DIV_64 6 92 #define MCO_PRE_DIV_128 7 93 94 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */ 95
