1 /* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ 8 9 /** Define system & low-speed clocks */ 10 #include "stm32_common_clocks.h" 11 12 /** Other fixed clocks. 13 * - CLKSLOWMUX: used to query slow clock tree frequency 14 * - CLK16MHZ: secondary clock for LPUART, SPI3/I2S and BLE 15 * - CLK32MHZ: secondary clock for SPI3/I2S and BLE 16 */ 17 #define STM32_SRC_CLKSLOWMUX (STM32_SRC_LSI + 1) 18 #define STM32_SRC_CLK16MHZ (STM32_SRC_CLKSLOWMUX + 1) 19 #define STM32_SRC_CLK32MHZ (STM32_SRC_CLK16MHZ + 1) 20 21 /** Bus clocks */ 22 #define STM32_CLOCK_BUS_AHB0 0x50 23 #define STM32_CLOCK_BUS_APB0 0x54 24 #define STM32_CLOCK_BUS_APB1 0x58 25 #define STM32_CLOCK_BUS_APB2 0x60 26 27 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB0 28 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 29 30 #define STM32_CLOCK_REG_MASK (0xFFFFU) 31 #define STM32_CLOCK_REG_SHIFT (0U) 32 #define STM32_CLOCK_SHIFT_MASK (0x3FU) 33 #define STM32_CLOCK_SHIFT_SHIFT (16U) 34 #define STM32_CLOCK_MASK_MASK (0x1FU) 35 #define STM32_CLOCK_MASK_SHIFT (22U) 36 #define STM32_CLOCK_VAL_MASK STM32_CLOCK_MASK_MASK 37 #define STM32_CLOCK_VAL_SHIFT (27U) 38 39 /** 40 * @brief STM32 clock configuration bit field 41 * 42 * @param reg Offset to target configuration register in RCC 43 * @param shift Position of field within RCC register (= field LSB's index) 44 * @param mask Mask of field in RCC register 45 * @param val Field value 46 * 47 * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ] 48 * @note 'shift' range: 0~63 [ 16 : 21 ] 49 * @note 'mask' range: 0x00~0x1F [ 22 : 26 ] 50 * @note 'val' range: 0x00~0x1F [ 27 : 31 ] 51 */ 52 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 53 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 54 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 55 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 56 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 57 58 /** @brief RCC_CFGR register offset */ 59 #define CFGR_REG 0x08 60 61 /** @brief RCC_APB2ENR register offset */ 62 #define APB2ENR_REG 0x60 63 64 /** @brief Device clk sources selection helpers */ 65 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */ 66 #define SPI2_I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG) /* WB06/WB07 only */ 67 /* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */ 68 #define SPI3_I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG) 69 70 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */ 71
