1 /*
2  * Copyright (c) 2022 Linaro Limited
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
8 
9 #include "stm32_common_clocks.h"
10 
11 /** Bus gatting clocks */
12 #define STM32_CLOCK_BUS_AHB1    0x014
13 #define STM32_CLOCK_BUS_APB2    0x018
14 #define STM32_CLOCK_BUS_APB1    0x01c
15 
16 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
17 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB1
18 
19 /** Domain clocks */
20 
21 /** System clock */
22 /* defined in stm32_common_clocks.h */
23 /** Fixed clocks  */
24 /* Low speed clocks defined in stm32_common_clocks.h */
25 #define STM32_SRC_HSI		(STM32_SRC_LSI + 1)
26 #define STM32_SRC_HSI14		(STM32_SRC_HSI + 1)
27 #define STM32_SRC_HSI48		(STM32_SRC_HSI14 + 1)
28 /** Bus clock */
29 #define STM32_SRC_PCLK		(STM32_SRC_HSI48 + 1)
30 /** PLL clock */
31 #define STM32_SRC_PLLCLK	(STM32_SRC_PCLK + 1)
32 
33 #define STM32_CLOCK_REG_MASK    0xFFU
34 #define STM32_CLOCK_REG_SHIFT   0U
35 #define STM32_CLOCK_SHIFT_MASK  0x1FU
36 #define STM32_CLOCK_SHIFT_SHIFT 8U
37 #define STM32_CLOCK_MASK_MASK   0x7U
38 #define STM32_CLOCK_MASK_SHIFT  13U
39 #define STM32_CLOCK_VAL_MASK    0x7U
40 #define STM32_CLOCK_VAL_SHIFT   16U
41 
42 /**
43  * @brief STM32 clock configuration bit field.
44  *
45  * - reg   (1/2/3)         [ 0 : 7 ]
46  * - shift (0..31)         [ 8 : 12 ]
47  * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
48  * - val   (0..7)          [ 16 : 18 ]
49  *
50  * @param reg RCC_CFGRx register offset
51  * @param shift Position within RCC_CFGRx.
52  * @param mask Mask for the RCC_CFGRx field.
53  * @param val Clock value (0, 1, ... 7).
54  */
55 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
56 	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
57 	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
58 	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
59 	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
60 
61 /** @brief RCC_CFGRx register offset */
62 #define CFGR1_REG               0x04
63 #define CFGR3_REG		0x30
64 
65 /** @brief RCC_BDCR register offset */
66 #define BDCR_REG		0x20
67 
68 /** @brief Device domain clocks selection helpers */
69 /** CFGR3 devices */
70 #define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
71 #define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
72 #define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
73 #define USB_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG)
74 #define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
75 #define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
76 /** BDCR devices */
77 #define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
78 
79 /** CFGR1 devices */
80 #define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
81 #define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
82 
83 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */
84