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Searched refs:DT_REG_SIZE (Results 1 – 25 of 143) sorted by relevance

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/Zephyr-latest/boards/snps/em_starterkit/
Darc_mpu_regions.c16 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
20 DT_REG_SIZE(DT_INST(0, arc_iccm)),
23 #if DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0
27 DT_REG_SIZE(DT_INST(0, arc_dccm)),
31 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
35 DT_REG_SIZE(DT_INST(0, arc_xccm)),
38 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
42 DT_REG_SIZE(DT_INST(0, arc_yccm)),
46 #if DT_REG_SIZE(DT_INST(0, mmio_sram)) > 0
50 DT_REG_SIZE(DT_INST(0, mmio_sram)),
/Zephyr-latest/boards/snps/nsim/arc_classic/
Darc_mpu_regions.c27 #if DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0
31 DT_REG_SIZE(DT_INST(0, arc_iccm)),
34 #if DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0
38 DT_REG_SIZE(DT_INST(0, arc_dccm)),
41 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
45 DT_REG_SIZE(DT_INST(0, arc_xccm)),
48 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
52 DT_REG_SIZE(DT_INST(0, arc_yccm)),
58 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
63 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
[all …]
/Zephyr-latest/boards/snps/emsdp/
Darc_mpu_regions.c15 DT_REG_SIZE(DT_INST(0, arc_iccm)),
20 DT_REG_SIZE(DT_INST(0, arc_dccm)),
23 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
26 DT_REG_SIZE(DT_INST(0, arc_xccm)),
30 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
33 DT_REG_SIZE(DT_INST(0, arc_yccm)),
39 DT_REG_SIZE(DT_INST(0, mmio_sram)),
/Zephyr-latest/boards/snps/iotdk/
Darc_mpu_regions.c15 DT_REG_SIZE(DT_INST(0, arc_iccm)),
20 DT_REG_SIZE(DT_INST(0, arc_dccm)),
23 #if DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0
26 DT_REG_SIZE(DT_INST(0, arc_xccm)),
30 #if DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0
33 DT_REG_SIZE(DT_INST(0, arc_yccm)),
/Zephyr-latest/soc/nxp/imx/imx9/imx93/a55/
Dmmu_regions.c21 MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
25 DT_REG_SIZE(DT_NODELABEL(ana_pll)),
29 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
40 DT_REG_SIZE(DT_NODELABEL(mu2_a)),
44 DT_REG_SIZE(DT_NODELABEL(outbox)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
47 DT_REG_SIZE(DT_NODELABEL(inbox)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
50 DT_REG_SIZE(DT_NODELABEL(stream)), MT_NORMAL | MT_P_RW_U_NA | MT_NS),
53 DT_REG_SIZE(DT_NODELABEL(host_ram)),
/Zephyr-latest/soc/espressif/esp32s3/
Dmemory.h11 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
17 #define SRAM2_SIZE DT_REG_SIZE(DT_NODELABEL(sram2))
84 #define AMP_COMM_SIZE DT_REG_SIZE(DT_NODELABEL(ipmmem0)) + DT_REG_SIZE(DT_NODELABEL(shm0)) + \
85 DT_REG_SIZE(DT_NODELABEL(ipm0)) + DT_REG_SIZE(DT_NODELABEL(mbox0))
103 #define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0))
105 #define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0))
/Zephyr-latest/soc/snps/arc_iot/
Dlinker.ld18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
24 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
26 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
31 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
33 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
40 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
42 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-latest/soc/snps/nsim/arc_classic/
Dlinker.ld15 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
17 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
25 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
27 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
31 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
33 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
38 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
40 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/include/zephyr/arch/arc/v2/
Dxy_mem.ld8 (DT_REG_SIZE(DT_INST(0, arc_xccm)) > 0)
10 #define XCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_xccm))
14 (DT_REG_SIZE(DT_INST(0, arc_yccm)) > 0)
16 #define YCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_yccm))
/Zephyr-latest/soc/espressif/esp32/
Dmemory.h10 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
15 #define SRAM1_SIZE DT_REG_SIZE(DT_NODELABEL(sram1))
23 #define SRAM2_DRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram2))
92 #define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0))
94 #define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0))
96 #define DCACHE1_SIZE DT_REG_SIZE(DT_NODELABEL(dcache1))
/Zephyr-latest/boards/qemu/arc/
Darc_mpu_regions.c26 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
32 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
53 #if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
57 DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
/Zephyr-latest/soc/snps/emsdp/
Dlinker.ld18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
26 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
28 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
36 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
38 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dlinker.ld15 #if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
16 …SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0…
19 #if (DT_REG_SIZE(DT_NODELABEL(hyperram0)) > 0) && !IS_CHOSEN_SRAM(hyperram0)
20 …hyperram0 (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(hyperram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL…
/Zephyr-latest/soc/snps/emsk/
Dlinker.ld20 (DT_REG_SIZE(DT_NODELABEL(ddr0)) > 0)
22 #define SRAM_SIZE DT_REG_SIZE(DT_NODELABEL(ddr0))
27 (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
29 #define ICCM_SIZE DT_REG_SIZE(DT_INST(0, arc_iccm))
37 (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
39 #define DCCM_SIZE DT_REG_SIZE(DT_INST(0, arc_dccm))
/Zephyr-latest/soc/snps/qemu_arc/
Dlinker.ld13 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
15 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
22 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
24 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dmmu_regions.c25 DT_REG_SIZE(DT_NODELABEL(ccm)),
30 DT_REG_SIZE(DT_NODELABEL(ana_pll)),
35 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
40 DT_REG_SIZE(DT_NODELABEL(rdc)),
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h13 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
16 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
26 #define HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE)
92 #define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm)))
99 #define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm)))
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
Dsoc.c22 DT_REG_SIZE(id),\
37 DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
45 DT_REG_SIZE(DT_NODELABEL(gem0)),
51 DT_REG_SIZE(DT_NODELABEL(gem1)),
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
Dsoc.c22 DT_REG_SIZE(id),\
37 DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
45 DT_REG_SIZE(DT_NODELABEL(gem0)),
51 DT_REG_SIZE(DT_NODELABEL(gem1)),
/Zephyr-latest/soc/intel/intel_socfpga/agilex/
Dmmu_regions.c16 DT_REG_SIZE(DT_NODELABEL(sysmgr)),
21 DT_REG_SIZE(DT_NODELABEL(clock)),
26 DT_REG_SIZE(DT_NODELABEL(uart0)),
/Zephyr-latest/drivers/memc/
Dmemc_nxp_flexram.c35 #define OCRAM_END (OCRAM_START + DT_REG_SIZE(OCRAM_DT_NODE))
42 #define DTCM_END (DTCM_START + DT_REG_SIZE(DTCM_DT_NODE))
49 #define ITCM_END (ITCM_START + DT_REG_SIZE(ITCM_DT_NODE))
66 BUILD_ASSERT((OCRAM_TOTAL) == DT_REG_SIZE(OCRAM_DT_NODE), "OCRAM node size is wrong");
75 BUILD_ASSERT((DTCM_TOTAL) == DT_REG_SIZE(DTCM_DT_NODE), "DTCM node size is wrong");
84 BUILD_ASSERT((ITCM_TOTAL) == DT_REG_SIZE(ITCM_DT_NODE), "ITCM node size is wrong");
145 if (ocram_addr >= DT_REG_SIZE(OCRAM_DT_NODE)) { in memc_flexram_set_ocram_magic_addr()
163 if (itcm_addr >= DT_REG_SIZE(ITCM_DT_NODE)) { in memc_flexram_set_itcm_magic_addr()
181 if (dtcm_addr >= DT_REG_SIZE(DTCM_DT_NODE)) { in memc_flexram_set_dtcm_magic_addr()
/Zephyr-latest/soc/espressif/esp32s2/
Dmemory.h58 #define ICACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(icache0))
60 #define DCACHE0_SIZE DT_REG_SIZE(DT_NODELABEL(dcache0))
62 #define DCACHE1_SIZE DT_REG_SIZE(DT_NODELABEL(dcache1))
/Zephyr-latest/soc/nxp/imx/imx9/imx91/
Dmmu_regions.c20 MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
24 DT_REG_SIZE(DT_NODELABEL(ana_pll)),
28 DT_REG_SIZE(DT_NODELABEL(iomuxc)),
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h16 #define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
19 #define L2_VIRTUAL_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0virtual)))
22 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
34 #define L3_MEM_SIZE (DT_REG_SIZE(DT_NODELABEL(imr1)))
167 #define L2_HSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(hsbpm)))
174 #define L2_LSBPM_SIZE (DT_REG_SIZE(DT_NODELABEL(lsbpm)))
/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
Dmmu_regions.c13 DT_REG_SIZE(DT_NODELABEL(clock)),
19 DT_REG_SIZE(DT_NODELABEL(sysmgr)),
39 DT_REG_SIZE(DT_NODELABEL(its)),

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