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Searched +full:tx +full:- +full:dma +full:- +full:channel (Results 1 – 25 of 202) sorted by relevance

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/Zephyr-latest/dts/bindings/i2s/
Dnxp,mcux-i2s.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP mcux SAI-I2S controller
6 compatible: "nxp,mcux-i2s"
8 include: [i2s-controller.yaml, pinctrl-device.yaml]
17 dma-names:
20 nxp,tx-dma-channel:
23 description: tx dma channel number
25 nxp,rx-dma-channel:
28 description: rx dma channel number
30 nxp,tx-sync-mode:
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/Zephyr-latest/drivers/dma/
DKconfig.xilinx_axi_dma1 # Xilinx AXI DMA configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Xilinx AXI DMA LogiCORE IP driver"
11 DMA driver for Xilinx AXI DMAs, usually found on FPGAs.
15 bool "Disable data cache while accessing Scatter-Gather Descriptors."
19 Disable dcache while operating on Scatter-Gather descriptors.
20 This allows the DMA to be used on architectures that do not provide
21 coherency for DMA accesses. If you are unsure whether you need this feature,
25 int "Number of transfer descriptors allocated for transmission (TX)."
29 The Xilinx AXI DMA uses a ring of in-memory DMA descriptors which reference
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Ddma_xilinx_axi_dma.c2 *@brief Driver for Xilinx AXI DMA.
7 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/drivers/dma.h>
40 /* internal DMA error, e.g., 0-length transfer */
54 /* masks for DMA registers */
59 /* interrupt timeout - trigger interrupt after X cycles when no transfer. Unit is 125 * */
62 /* irqthreshold - this can be used to generate interrupts after X completed packets */
76 /* DMA ignores completed bit in SG descriptor and overwrites descriptors */
78 /* use AXI fixed burst instead of incrementing burst for TX transfers, e.g., useful for reading a */
84 /* run-stop */
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/Zephyr-latest/dts/bindings/mmc/
Dst,stm32-sdmmc.yaml3 compatible: "st,stm32-sdmmc"
5 include: [mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 cd-gpios:
24 type: phandle-array
27 pwr-gpios:
28 type: phandle-array
31 bus-width:
38 - 1
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/Zephyr-latest/dts/bindings/spi/
Datmel,sam-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam-spi"
9 - name: spi-controller.yaml
10 - name: pinctrl-device.yaml
25 Connects TX to RX internally creating a loop back connection. Useful
30 TX & RX dma specifiers. Each specifier will have a phandle
31 reference to the dma controller, the channel number, and peripheral
32 trigger source. The channel number is arbitrary but must not be
35 For example dmas for TX and RX may look like
38 dma-names:
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Dinfineon,xmc4xxx-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "infineon,xmc4xxx-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
14 miso-src:
23 - "DX0A"
24 - "DX0B"
25 - "DX0C"
26 - "DX0D"
27 - "DX0E"
28 - "DX0F"
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Datmel,sam0-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-spi"
9 - name: spi-controller.yaml
10 - name: pinctrl-device.yaml
19 clock-names:
34 Optional TX & RX dma specifiers. Each specifier will have a phandle
35 reference to the dmac controller, the channel number, and peripheral
38 For example dmas for TX, RX on SERCOM3
41 dma-names:
43 Required if the dmas property exists. This should be "tx" and "rx"
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/Zephyr-latest/dts/bindings/serial/
Dinfineon,xmc4xxx-uart.yaml3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 input-src:
20 - "DX0A"
21 - "DX0B"
22 - "DX0C"
23 - "DX0D"
24 - "DX0E"
25 - "DX0F"
26 - "DX0G"
[all …]
/Zephyr-latest/dts/bindings/dma/
Datmel,sam0-dmac.yaml1 description: Atmel SAM0 DMA controller
3 compatible: "atmel,sam0-dmac"
5 include: dma-controller.yaml
14 "#dma-cells":
17 # #dma-cells : Must be <2>.
18 # The 1st cell specifies the DMAC channel to be used for the data transfer.
19 # This channel should be unique between all peripherals that are using the
26 # Example of devicetree dma channel configuration:
29 # /* Configure DMA channels for async operation */
31 # dma-names = "rx", "tx";
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Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller for the stm32U5 soc family
7 It is present on stm32U5 devices as a GP DMA
9 DMA clients connected to the STM32 DMA controller must use a three-cell
10 specifier for each channel.
12 Tx using channel 0 with request 7
13 Rx using channel 1 with request 6
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
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Dandestech,atcdmac300.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
29 Andes DMA controller
30 channel: a phandle to the DMA controller plus the following four integer cells:
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Dmicrochip,xec-dmac.yaml1 description: Microchip XEC DMA controller
3 compatible: "microchip,xec-dmac"
5 include: dma-controller.yaml
24 aggregated-girq:
27 If DMA driver uses aggregated interrupt mode
30 "#dma-cells":
33 "pcr-cells":
37 "girq-cells":
41 # #dma-cells : Must be <2>.
42 # The 1st cell specifies the DMAC channel to be used for the data transfer.
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Dst,stm32-dma-v2bis.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
7 This DMA controller includes several channels with different requests.
8 All the requests ar ORed before entering the DMA, so that only one request
10 DMA clients connected to the STM32 DMA controller must use the format
11 described in the dma.txt file, using a 2-cell specifier for each
12 channel: a phandle to the DMA controller plus the following four integer cells:
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
15 A name custom DMA flags for channel configuration is used
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Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller
7 channel: Select channel for data transmitting
9 config: A 32bit mask specifying the DMA channel configuration
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
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Darm,dma-pl330.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PL330 DMA Controller
7 A phandle to the DMA controller plus "channel" integer cell specifying
8 channel to be used for data transfer
10 Example for pl330 DMA Controller
12 compatible = "arm,dma-pl330";
14 dma-channels = <8>;
15 #dma-cells = <1>;
18 If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
20 compatible = "brcm,iproc-pcie-ep";
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Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V1)
8 This DMA controller includes FIFO control registers.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 channel: a phandle to the DMA controller plus the following four integer cells:
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
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Dst,stm32-dma-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2)
8 This DMA controller includes several channels with different requests.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a 3-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. channel: the dma stream from 1 to <dma-requests>
[all …]
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
7 channel: Select channel for data transmitting
9 slot: Select peripheral to connect DMA
11 config: A 32bit mask specifying the DMA channel configuration
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
[all …]
/Zephyr-latest/dts/bindings/i3c/
Dst,stm32-i3c.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "st,stm32-i3c"
9 include: [i3c-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
18 pinctrl-names:
26 Optional DMA channel specifier, required for DMA transactions.
28 dma-names:
30 DMA channel name. If DMA should be used, expected value is "rx" "tx" "tc" "rs".
33 dma-names = "rx", "tx", "tc", "rs";
/Zephyr-latest/dts/bindings/qspi/
Dst,stm32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
9 pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
14 dma-names = "tx_rx";
19 compatible: "st,stm32-qspi"
21 include: [base.yaml, pinctrl-device.yaml]
32 pinctrl-0:
35 pinctrl-names:
40 Optional DMA channel specifier. If DMA should be used, specifier should
41 hold a phandle reference to the dma controller (not the DMAMUX even if present),
42 the channel number, the slot number, channel configuration and finally features.
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/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp32s3-xtensa-intmux.h4 * SPDX-License-Identifier: Apache-2.0
51 #define SPI2_DMA_INTR_SOURCE 44 /* interrupt of SPI2 DMA, level*/
52 #define SPI3_DMA_INTR_SOURCE 45 /* interrupt of SPI3 DMA, level*/
72 #define DMA_IN_CH0_INTR_SOURCE 66 /* interrupt of general DMA RX channel 0, LEVEL*/
73 #define DMA_IN_CH1_INTR_SOURCE 67 /* interrupt of general DMA RX channel 1, LEVEL*/
74 #define DMA_IN_CH2_INTR_SOURCE 68 /* interrupt of general DMA RX channel 2, LEVEL*/
75 #define DMA_IN_CH3_INTR_SOURCE 69 /* interrupt of general DMA RX channel 3, LEVEL*/
76 #define DMA_IN_CH4_INTR_SOURCE 70 /* interrupt of general DMA RX channel 4, LEVEL*/
77 #define DMA_OUT_CH0_INTR_SOURCE 71 /* interrupt of general DMA TX channel 0, LEVEL*/
78 #define DMA_OUT_CH1_INTR_SOURCE 72 /* interrupt of general DMA TX channel 1, LEVEL*/
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/Zephyr-latest/dts/bindings/arm/
Datmel,sam-ssc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam-ssc"
9 - name: base.yaml
10 - name: pinctrl-device.yaml
25 TX & RX dma specifiers. Each specifier will have a phandle
26 reference to the dma controller, the channel number, and peripheral
29 For example dmas for TX, RX would look like
32 dma-names:
35 This should be "tx" and "rx" to match the dmas property.
38 dma-names = "tx", "rx";
/Zephyr-latest/drivers/i2c/
DKconfig.dw2 # SPDX-License-Identifier: Apache-2.0
18 bool "Use I2C integrated DMA for asynchronous transfer"
20 select DMA
23 This option enables I2C DMA feature to be used for asynchronous
24 data transfers. All Tx operations are done using dma channel 0 and
25 all Rx operations are done using dma channel 1.
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt11xx_cm4.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 /delete-node/ cpu@0;
23 /delete-node/ dma-controller@40070000;
26 compatible = "mmio-sram";
31 compatible = "zephyr,memory-region", "mmio-sram";
33 zephyr,memory-region = "SRAM1";
41 compatible = "nxp,imx-gpio";
44 gpio-controller;
45 #gpio-cells = <2>;
49 compatible = "nxp,imx-gpio";
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/Zephyr-latest/dts/bindings/i2c/
Datmel,sam0-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-i2c"
9 - name: i2c-controller.yaml
10 - name: pinctrl-device.yaml
22 clock-names:
27 Optional TX & RX dma specifiers. Each specifier will have a phandle
28 reference to the dmac controller, the channel number, and peripheral
31 For example dmas for TX, RX on SERCOM3
34 dma-names:
36 Required if the dmas property exists. This should be "tx" and "rx"
[all …]

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