1# Xilinx AXI DMA configuration options
2
3# Copyright (c) 2023 CISPA Helmholtz Center for Information Security gGmbH
4# SPDX-License-Identifier: Apache-2.0
5
6config DMA_XILINX_AXI_DMA
7	bool "Xilinx AXI DMA LogiCORE IP driver"
8	default y
9	depends on DT_HAS_XLNX_AXI_DMA_1_00_A_ENABLED || DT_HAS_XLNX_ETH_DMA_ENABLED
10	help
11	  DMA driver for Xilinx AXI DMAs, usually found on FPGAs.
12
13
14config DMA_XILINX_AXI_DMA_DISABLE_CACHE_WHEN_ACCESSING_SG_DESCRIPTORS
15	bool "Disable data cache while accessing Scatter-Gather Descriptors."
16	depends on DMA_XILINX_AXI_DMA
17	default n
18	help
19		Disable dcache while operating on Scatter-Gather descriptors.
20		This allows the DMA to be used on architectures that do not provide
21		coherency for DMA accesses. If you are unsure whether you need this feature,
22		you should select n here.
23
24config DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX
25	int "Number of transfer descriptors allocated for transmission (TX)."
26	depends on DMA_XILINX_AXI_DMA
27	default 16
28	help
29		The Xilinx AXI DMA uses a ring of in-memory DMA descriptors which reference
30		the buffers containing the network packets and control and status information.
31		Increasing the number of descriptors increases the amount of packets in flight,
32		which benefits performance, while increasing memory usage.
33
34config DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX
35	int "Number of transfer descriptors allocated for reception (RX)."
36	depends on DMA_XILINX_AXI_DMA
37	default 16
38	help
39		The AXI DMA driver currently allocates a single DMA descriptor for each RX transfer,
40		because transfers need to be started by the upstream driver.
41
42choice
43	prompt "IRQs to lock when manipulating per-channel data structures during dma_start."
44	depends on DMA_XILINX_AXI_DMA
45	default DMA_XILINX_AXI_DMA_LOCK_ALL_IRQS
46
47config DMA_XILINX_AXI_DMA_LOCK_ALL_IRQS
48	bool "Lock all IRQs"
49	help
50		Lock all interrupts (including, e.g., timers and scheduler) when modifying channel data
51		during dma_start.
52		This is required when calling dma_start outside of the TX/RX callbacks.
53		This is the safest option and the default, select this if you are unsure.
54
55config DMA_XILINX_AXI_DMA_LOCK_DMA_IRQS
56	bool "Lock TX and RX IRQs"
57	help
58		Lock all interrupts of this DMA device when modifying channel data during dma_start.
59		This is only safe when dma_start is only called from the TX/RX callbacks (and possibly
60		once directly after initialization of the DMA).
61
62config DMA_XILINX_AXI_DMA_LOCK_CHANNEL_IRQ
63	bool "Lock IRQs of the DMA channel"
64	help
65		Only lock the interrupt of the DMA channel whose data are to be modified during dma_start.
66		Only select this when you can guarantee that dma_start is only called from the callback
67		registered for the same channel.
68
69endchoice
70
71config DMA_XILINX_AXI_DMA_POLL_INTERVAL
72	int "Period of the timer used for polling the DMA in milliseconds"
73	depends on DMA_XILINX_AXI_DMA
74	default 100
75	help
76		On certain platforms (e.g., RISC-V), the DMA driver can sometimes miss interrupts.
77		This can cause the DMA driver to stop processing completed transactions.
78		In order to prevent this, the DMA driver periodically polls the DMA's registers and
79		determines whether it needs to handle outstanding transactions.
80		This configuration controls how often this happens.
81		Choose a larger value to minimize overhead and a smaller value to minimize
82		worst-case latency.
83
84config DMA_XILINX_AXI_DMA_INTERRUPT_THRESHOLD
85	int "Number of completed transactions after which to trigger an interrupt"
86	depends on DMA_XILINX_AXI_DMA
87	range 1 255
88	default 8
89	help
90		Number of completed transactions after which to trigger an interrupt.
91		Decrease to minimize latency, increase to minimize overhead introduced by interrupts.
92
93config DMA_XILINX_AXI_DMA_INTERRUPT_TIMEOUT
94	int "Timeout for triggering an interrupt"
95	depends on DMA_XILINX_AXI_DMA
96	range 0 255
97	default 16
98	help
99		Trigger an interrupt at the latest after
100		CONFIG_DMA_XILINX_AXI_DMA_INTERRUPT_TIMEOUT * 125 * DMA_CLOCK_PERIOD cycles.
101		This is useful in conjunction with DMA_XILINX_AXI_DMA_INTERRUPT_THRESHOLD - the DMA
102		can raise an interrupt before the threshold is reached, minimizing latency in scenarios
103		where only few transactions per second are completed.
104		Set to 0 to disable this feature, i.e., interrupts will only be raised when the threshold
105		has been reached.
106