1# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com> 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 STM32 DMA controller (V1) 6 7 It is present on stm32 devices like stm32F4 or stm32F2. 8 This DMA controller includes FIFO control registers. 9 DMA clients connected to the STM32 DMA controller must use the format 10 described in the dma.txt file, using a four-cell specifier for each 11 channel: a phandle to the DMA controller plus the following four integer cells: 12 1. channel: the dma stream from 0 to <dma-requests> 13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR 14 this value is 0 for Memory-to-memory transfers 15 or a value between <1> .. <dma-generators> (not supported yet) 16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests> 17 3. channel-config: A 32bit mask specifying the DMA channel configuration 18 which is device dependent. See stm32_dma.h: 19 -bit 6-7 : Direction (see dma.h) 20 0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM 21 0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH 22 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM 23 0x3: reserved for PERIPH to PERIPH 24 -bit 9 : Peripheral Increment Address 25 0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers 26 0x1: STM32_DMA_PERIPH_INC: increment address between transfers 27 -bit 10 : Memory Increment Address 28 0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers 29 0x1: STM32_DMA_MEM_INC: increment address between transfers 30 -bit 11-12 : Peripheral data size 31 0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits) 32 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits) 33 0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits) 34 0x3: reserved 35 -bit 13-14 : Memory data size 36 0x0: STM32_DMA_MEM_8BITS: Byte (8 bits) 37 0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits) 38 0x2: STM32_DMA_MEM_32BITS: Word (32 bits) 39 0x3: reserved 40 -bit 15: Peripheral Increment Offset Size 41 0x0: STM32_DMA_OFFSET_LINKED_BUS: offset size is linked to the peripheral bus width 42 0x1: STM32_DMA_OFFSET_FIXED_4: offset size is fixed to 4 (32-bit alignment) 43 -bit 16-17 : Priority level 44 0x0: STM32_DMA_PRIORITY_LOW: low 45 0x1: STM32_DMA_PRIORITY_MEDIUM: medium 46 0x2: hSTM32_DMA_PRIORITY_HIGH: high 47 0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high 48 4. features: A 32bit bitfield value specifying DMA features 49 -bit 0-1: DMA FIFO threshold selection 50 0x0: STM32_DMA_FIFO_1_4: 1/4 full FIFO 51 0x1: STM32_DMA_FIFO_HALF: 1/2 full FIFO 52 0x2: STM32_DMA_FIFO_3_4: 3/4 full FIFO 53 0x3: STM32_DMA_FIFO_FULL: full FIFO 54 55 Example of dma usual combination for peripheral transfer 56 #define STM32_DMA_PERIPH_TX (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC) 57 #define STM32_DMA_PERIPH_RX (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC) 58 59 examples for stm32f411 60 dma2: dma-controller@40020400 { 61 compatible = "st,stm32-dma-v1"; 62 ... 63 st,mem2mem; 64 dma-requests = <7>; 65 status = "disabled"; 66 }; 67 68 For the client part, example for stm32f411 on DMA2 instance 69 Tx using stream 5 on channel 3 (stream 2 on channel 2 is also possible) 70 Rx using stream 2 on channel 3 (stream 0 on channel 3 is also possible) 71 spi1 { 72 dmas = <&dma2 5 3 STM32_DMA_PERIPH_TX STM32_DMA_FIFO_FULL>, 73 <&dma2 2 3 STM32_DMA_PERIPH_RX STM32_DMA_FIFO_FULL>; 74 dma-names = "tx", "rx"; 75 }; 76 77compatible: "st,stm32-dma-v1" 78 79include: st,stm32-dma.yaml 80 81properties: 82 "#dma-cells": 83 const: 4 84 85# Parameter syntax of stm32 follows the dma client dts syntax 86# in the Linux kernel declared in 87# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml 88 89dma-cells: 90 - channel 91 - slot 92 - channel-config 93 - features 94
