1# Copyright (c) 2022, TOKITA Hiroshi <tokita.hiroshi@gmail.com> 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 GD32 DMA controller 6 7 channel: Select channel for data transmitting 8 9 config: A 32bit mask specifying the DMA channel configuration 10 - bit 6-7: Direction (see dma.h) 11 - 0x0: MEMORY to MEMORY 12 - 0x1: MEMORY to PERIPH 13 - 0x2: PERIPH to MEMORY 14 - 0x3: reserved for PERIPH to PERIPH 15 16 - bit 9: Peripheral address increase 17 - 0x0: no address increment between transfers 18 - 0x1: increment address between transfers 19 20 - bit 10: Memory address increase 21 - 0x0: no address increase between transfers 22 - 0x1: increase address between transfers 23 24 - bit 11-12: Peripheral data width 25 - 0x0: 8 bits 26 - 0x1: 16 bits 27 - 0x2: 32 bits 28 - 0x3: reserved 29 30 - bit 13-14: Memory data width 31 - 0x0: 8 bits 32 - 0x1: 16 bits 33 - 0x2: 32 bits 34 - 0x3: reserved 35 36 - bit 15: Peripheral Increment Offset Size 37 - 0x0: offset size is linked to the peripheral bus width 38 - 0x1: offset size is fixed to 4 (32-bit alignment) 39 40 - bit 16-17: Priority 41 - 0x0: low 42 - 0x1: medium 43 - 0x2: high 44 - 0x3: very high 45 46 Example of devicetree configuration 47 48 &spi0 { 49 status = "okay"; 50 pinctrl-0 = <&spi0_default>; 51 pinctrl-names = "default"; 52 cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; 53 54 dmas = <&dma0 3 0>, <&dma0 5 GD32_DMA_PRIORITY_HIGH>; 55 dma-names = "rx", "tx"; 56 }; 57 58 "spi0" uses dma0 for transmitting and receiving in the example. 59 Each is named "rx" and "tx". 60 The channel cell assigns channel 3 to receive and channel 5 to transmit. 61 The config cell can take various configs. 62 But the setting used depends on each driver implementation. 63 Set the priority for the transmitting channel as HIGH, LOW(the default) for receive channel. 64 65compatible: "gd,gd32-dma" 66 67include: ["gd,gd32-dma-base.yaml"] 68 69properties: 70 "#dma-cells": 71 const: 2 72 73dma-cells: 74 - channel 75 - config 76