1description: Microchip XEC DMA controller
2
3compatible: "microchip,xec-dmac"
4
5include: dma-controller.yaml
6
7properties:
8  reg:
9    required: true
10
11  interrupts:
12    required: true
13
14  pcrs:
15    type: array
16    required: true
17    description: PCR register index and bit position
18
19  girqs:
20    type: array
21    required: true
22    description: Encoded interrupt information
23
24  aggregated-girq:
25    type: phandle
26    description: |
27      If DMA driver uses aggregated interrupt mode
28      provide the handle to the GIRQ.
29
30  "#dma-cells":
31    const: 2
32
33  "pcr-cells":
34    type: int
35    const: 2
36
37  "girq-cells":
38    type: int
39    const: 2
40
41# #dma-cells : Must be <2>.
42# The 1st cell specifies the DMAC channel to be used for the data transfer.
43#   This channel should be unique between all peripherals that are using the
44#   DMAC instance.
45# The 2nd cell defines the peripheral trigger which is the source of the transfer.
46#   For details on trigger selection and trigger modes, refer to
47#   "Transfer Triggers and Actions".
48#   See the SoC's reference manual for all the supported request sources.
49#
50# Example of devicetree dma channel configuration:
51#
52# &sercom3 {
53#     /* Configure DMA channels for async operation */
54#     dmas = <&dmac 10 7>, <&dmac 11 8>;
55#     dma-names = "rx", "tx";
56# };
57#
58# In above fragment 10 and 11 represents the different channels used to
59# transfer data between peripheral and ram. The numbers 7/8 are, for instance,
60# uart_rx/tx peripheral trigger for sercom3.
61dma-cells:
62  - channel
63  - trigsrc
64
65pcr-cells:
66  - regidx
67  - bitpos
68
69girq-cells:
70  - girqno
71  - girqpos
72