1# Copyright (c) 2021, STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
6
7  This DMA controller includes several channels with different requests.
8  All the requests ar ORed before entering the DMA, so that only one request
9  must be enabled at a time.
10  DMA clients connected to the STM32 DMA controller must use the format
11  described in the dma.txt file, using a 2-cell specifier for each
12  channel: a phandle to the DMA controller plus the following four integer cells:
13    1. channel: the dma stream from 1 to <dma-requests>
14    2. channel-config: A 32bit mask specifying the DMA channel configuration
15    A name custom DMA flags for channel configuration is used
16    which is device dependent see stm32_dma.h:
17      -bit 5 : DMA  cyclic mode config
18                0x0: STM32_DMA_MODE_NORMAL
19                0x1: STM32_DMA_MODE_CYCLIC
20      -bit 6-7 : Direction (see dma.h)
21                0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
22                0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
23                0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
24                0x3: reserved for PERIPH to PERIPH
25      -bit 9 : Peripheral Increment Address
26               0x0: STM32_DMA_PERIPH_NO_INC: no address increment between transfers
27               0x1: STM32_DMA_PERIPH_INC: increment address between transfers
28      -bit 10 : Memory Increment Address
29               0x0: STM32_DMA_MEM_NO_INC: no address increment between transfers
30               0x1: STM32_DMA_MEM_INC: increment address between transfers
31      -bit 11-12 : Peripheral data size
32               0x0: STM32_DMA_PERIPH_8BITS: Byte (8 bits)
33               0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
34               0x2: STM32_DMA_PERIPH_32BITS: Word (32 bits)
35               0x3: reserved
36      -bit 13-14 : Memory data size
37               0x0: STM32_DMA_MEM_8BITS: Byte (8 bits)
38               0x1: STM32_DMA_MEM_16BITS: Half-word (16 bits)
39               0x2: STM32_DMA_MEM_32BITS: Word (32 bits)
40               0x3: reserved
41      -bit 15: Reserved
42      -bit 16-17 : Priority level
43               0x0: STM32_DMA_PRIORITY_LOW: low
44               0x1: STM32_DMA_PRIORITY_MEDIUM: medium
45               0x2: STM32_DMA_PRIORITY_HIGH: high
46               0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
47
48  Example of dma usual combination for peripheral transfer
49       #define STM32_DMA_PERIPH_TX	(STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC)
50       #define STM32_DMA_PERIPH_RX	(STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC)
51
52  Example of dma node for stm32f103
53     dma1: dma-controller@40020400 {
54         compatible = "st,stm32-dma-v2bis";
55         ...
56         dma-requests = <7>;
57         status = "disabled";
58        };
59
60  For the client part, example for stm32f103 on DMA1 instance
61    Tx using channel 3
62    Rx using channel 2
63    spi1 {
64     compatible = "st,stm32-spi";
65     dmas = <&dma1 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
66            <&dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
67     dma-names = "tx", "rx";
68    };
69
70compatible: "st,stm32-dma-v2bis"
71
72include:
73  - name: st,stm32-dma.yaml
74
75properties:
76  "#dma-cells":
77    const: 2
78
79# Parameter syntax of stm32 follows the dma client dts syntax
80# in the Linux kernel declared in
81# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
82
83dma-cells:
84  - channel
85  - channel-config
86