1# Copyright (c) 2022 STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 DMA controller for the stm32U5 soc family
6
7  It is present on stm32U5 devices as a GP DMA
8  This controller includes several channels with different requests.
9  DMA clients connected to the STM32 DMA controller must use a three-cell
10  specifier for each channel.
11  For the client part, example for stm32u585 on GPDMA1 instance
12    Tx using channel 0 with request 7
13    Rx using channel 1 with request 6
14    spi1 {
15     dmas = <&gpdma1 0 7 0x10440>,
16            <&gpdma1 1 6 0x10480>;
17     dma-names = "tx", "rx";
18    };
19  It is a phandle to the DMA controller plus the following three integer cells
20    1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21    2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22    the slot is a value between <0> .. (<dma-requests> - 1).
23    3. channel-config: A 32bit mask specifying the DMA channel configuration
24    which is device dependent:
25        -bit 6-7 : Direction  (see dma.h)
26               0x0: MEM to MEM
27               0x1: MEM to PERIPH
28               0x2: PERIPH to MEM
29               0x3: reserved for PERIPH to PERIPH
30        -bit 9 : Peripheral Increment Address
31               0x0: no address increment between transfers
32               0x1: increment address between transfers
33        -bit 10 : Memory Increment Address
34               0x0: no address increment between transfers
35               0x1: increment address between transfers
36        -bit 11-12 : Peripheral data size
37               0x0: Byte (8 bits)
38               0x1: Half-word (16 bits)
39               0x2: Word (32 bits)
40               0x3: reserved
41        -bit 13-14 : Memory data size
42               0x0: Byte (8 bits)
43               0x1: Half-word (16 bits)
44               0x2: Word (32 bits)
45               0x3: reserved
46        -bit 15: Reserved
47        -bit 16-17 : Priority level
48               0x0: low
49               0x1: medium
50               0x2: high
51               0x3: very high
52
53compatible: "st,stm32u5-dma"
54
55include: st,stm32-dma.yaml
56
57properties:
58  "#dma-cells":
59    const: 3
60
61dma-cells:
62  - channel
63  - slot
64  - channel-config
65