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/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S0x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m33f";
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
Dnxp_lpc51u68.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m0+";
27 compatible = "nxp,lpc-syscon";
[all …]
Dnxp_lpc55S2x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
23 zephyr,flash-controller = &iap;
27 #address-cells = <1>;
[all …]
Dnxp_lpc54xxx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
16 gpio-0 = &gpio0;
17 gpio-1 = &gpio1;
18 mailbox-0 = &mailbox0;
22 zephyr,flash-controller = &iap;
26 #address-cells = <1>;
[all …]
Dnxp_lpc55S1x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33f";
[all …]
Dnxp_lpc55S3x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
Dnxp_lpc55S6x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <arm/armv8-m.dtsi>
16 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
24 zephyr,flash-controller = &iap;
[all …]
/Zephyr-latest/dts/bindings/reset/
Dst,stm32-rcc-rctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock Control (RCC) node.
6 This node is in charge of reset control for AHB (Advanced High Performance)
9 To specify the reset line in a peripheral, the standard resets property needs
19 RCC reset cells are available in
20 include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
22 compatible: "st,stm32-rcc-rctl"
24 include: [reset-controller.yaml, base.yaml]
27 "#reset-cells":
30 set-bit-to-deassert:
[all …]
Dgd,gd32-rctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the reset controller (RCTL).
9 To specify the reset line in a peripheral, the standard resets property needs
19 Predefined RCU reset cells are available in
20 include/zephyr/dts-bindings/reset/gd32{xxx}.h header files, where {xxx}
23 compatible: "gd,gd32-rctl"
25 include: [reset-controller.yaml, base.yaml]
28 "#reset-cells":
[all …]
Dnxp,lpc-syscon-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: LPC SYSCON Peripheral reset controller
6 compatible: "nxp,lpc-syscon-reset"
8 include: [reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
15 - id
Daspeed,ast10x0-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Aspeed AST10X0 Reset Controller
6 compatible: "aspeed,ast10x0-reset"
8 include: [base.yaml, reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
15 - id
Draspberrypi,pico-reset.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Raspberry Pi Pico Reset Controller
6 compatible: "raspberrypi,pico-reset"
8 include: [base.yaml, reset-controller.yaml]
13 reg-width:
15 description: The width of the reset registers in bytes. Default is 4 bytes.
16 active-low:
18 description: Set if reset is active low. Default is 0, which means active-high.
19 "#reset-cells":
[all …]
Dintel,socfpga-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Intel SoC FPGA Reset Controller
6 compatible: "intel,socfpga-reset"
8 include: [base.yaml, reset-controller.yaml]
13 active-low:
15 description: Add this property in dts node if the reset line is active_low, otherwise do not
17 "#reset-cells":
20 reset-cells:
21 - id
Dnxp,rstctl.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP RSTCTL Peripheral reset controller
8 include: [reset-controller.yaml, base.yaml]
14 "#reset-cells":
17 reset-cells:
18 - id
Dnuvoton,npcx-rst.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NPCX Reset Controller
6 compatible: "nuvoton,npcx-rst"
8 include: [reset-controller.yaml, base.yaml]
14 "#reset-cells":
17 reset-cells:
18 - id
Dnuvoton,numaker-rst.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, Numaker-RESET
6 compatible: "nuvoton,numaker-rst"
8 include: [reset-controller.yaml, base.yaml]
14 "#reset-cells":
17 reset-cells:
18 - id
Dreset-controller.yaml1 # Copyright (c) 2022 Andrei-Edward Popa <andrei.popa105@yahoo.com>
2 # SPDX-License-Identifier: Apache-2.0
4 description: Reset Controller
7 "#reset-cells":
11 Number of cells in reset property. There must be a cell
/Zephyr-latest/tests/drivers/build_all/dac/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
37 #io-channel-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/adc.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
12 #include <zephyr/dt-bindings/reset/rp2350_reset.h>
21 die-temp0 = &die_temp;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
Drp2040.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/regulator/rpi_pico.h>
13 #include <zephyr/dt-bindings/reset/rp2040_reset.h>
28 die-temp0 = &die_temp;
32 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi2 * SPDX-License-Identifier: Apache-2.0
8 #include <arm64/armv8-a.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
11 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
16 #address-cells = <1>;
17 #size-cells= <0>;
21 compatible = "arm,cortex-a55";
22 enable-method = "psci";
28 compatible = "arm,cortex-a55";
[all …]
/Zephyr-latest/dts/bindings/test/
Dvnd,reset.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Test Reset Controller
6 compatible: "vnd,reset"
8 include: [base.yaml, reset-controller.yaml]
11 reg-width:
14 "#reset-cells":
17 reset-cells:
18 - id
/Zephyr-latest/dts/bindings/i2c/
Dti,tca954x-base.yaml2 # SPDX-License-Identifier: Apache-2.0
18 #address-cells = <1>;
19 #size-cells = <0>;
20 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
23 compatible: "ti,tca9546a-channel"
25 #address-cells = <1>;
26 #size-cells = <0>;
35 compatible: "ti,tca9546a-channel"
37 #address-cells = <1>;
38 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dnxp,pcal64xxa-base.yaml3 # SPDX-License-Identifier: Apache-2.0
5 include: [i2c-device.yaml, gpio-controller.yaml]
8 int-gpios:
9 type: phandle-array
11 GPIO connected to the controller INT pin. This pin is active-low.
13 reset-gpios:
14 type: phandle-array
16 GPIO connected to the controller RESET pin. This pin is active-low.
18 no-auto-reset:
21 This flag disables the automatic reset, which allows the implementation
[all …]
/Zephyr-latest/tests/drivers/build_all/video/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
42 reset-gpios = <&test_gpio 0 0>;
[all …]

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