Lines Matching +full:reset +full:- +full:cells
2 * SPDX-License-Identifier: Apache-2.0
8 #include <arm64/armv8-a.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/reset/intel_socfpga_reset.h>
11 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
16 #address-cells = <1>;
17 #size-cells= <0>;
21 compatible = "arm,cortex-a55";
22 enable-method = "psci";
28 compatible = "arm,cortex-a55";
29 enable-method = "psci";
35 compatible = "arm,cortex-a76";
36 enable-method = "psci";
42 compatible = "arm,cortex-a76";
43 enable-method = "psci";
48 gic: interrupt-controller@1d000000 {
49 compatible = "arm,gic-v3", "arm,gic";
52 interrupt-controller;
53 #interrupt-cells = <4>;
55 #address-cells = <1>;
56 #size-cells = <1>;
58 its: msi-controller@1d040000 {
59 compatible = "arm,gic-v3-its";
66 compatible = "arm,armv8-timer";
67 interrupt-parent = <&gic>;
80 compatible = "intel,agilex5-clock";
82 #clock-cells = <1>;
86 compatible = "arm,psci-1.1";
102 compatible = "altr,socfpga-agilex-bridge";
107 reg-shift = <2>;
109 interrupt-parent = <&gic>;
111 interrupt-names = "irq_0";
113 resets = <&reset RSTMGR_UART0_RSTLINE>;
117 reset: reset-controller@10D11000 { label
118 compatible = "intel,socfpga-reset";
120 active-low;
121 #reset-cells = <1>;
129 reg-names = "reg_base", "combo_phy";
130 clock-frequency = <200000000>;
132 resets = <&reset RSTMGR_SDMMC_RSTLINE>,
133 <&reset RSTMGR_SDMMCECC_RSTLINE>,
134 <&reset RSTMGR_SOFTPHY_RSTLINE>;
139 compatible = "snps,dw-timers";
140 interrupt-parent = <&gic>;
145 resets = <&reset RSTMGR_SPTIMER0_RSTLINE>;
150 compatible = "snps,dw-timers";
151 interrupt-parent = <&gic>;
156 resets = <&reset RSTMGR_SPTIMER1_RSTLINE>;
161 compatible = "snps,dw-timers";
162 interrupt-parent = <&gic>;
167 resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>;
172 compatible = "snps,dw-timers";
173 interrupt-parent = <&gic>;
178 resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>;
182 compatible = "snps,designware-watchdog";
184 clock-frequency = <100000000>;
185 resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>;
190 compatible = "snps,designware-watchdog";
192 clock-frequency = <100000000>;
193 resets = <&reset RSTMGR_WATCHDOG1_RSTLINE>;
198 compatible = "snps,designware-watchdog";
200 clock-frequency = <100000000>;
201 resets = <&reset RSTMGR_WATCHDOG2_RSTLINE>;
206 compatible = "snps,designware-watchdog";
208 clock-frequency = <100000000>;
209 resets = <&reset RSTMGR_WATCHDOG3_RSTLINE>;
214 compatible = "snps,designware-watchdog";
216 clock-frequency = <100000000>;
217 resets = <&reset RSTMGR_WATCHDOG4_RSTLINE>;
222 compatible = "intel,socfpga-agilex-sip-smc";
225 zephyr,num-clients = <2>;
233 reg-names = "nand_reg","sdma";
234 interrupt-parent = <&gic>;
236 resets = <&reset RSTMGR_NAND_RSTLINE>,
237 <&reset RSTMGR_SOFTPHY_RSTLINE>;
238 block-size = <0x20000>;
239 data-rate-mode = <0>;
244 compatible = "snps,designware-dma-axi";
245 #dma-cells = <1>;
247 interrupt-parent = <&gic>;
256 dma-channels = <4>;
257 resets = <&reset RSTMGR_DMA_RSTLINE>;
262 compatible = "snps,designware-dma-axi";
263 #dma-cells = <1>;
265 interrupt-parent = <&gic>;
274 dma-channels = <4>;
275 resets = <&reset RSTMGR_DMA_RSTLINE>;
281 interrupt-parent = <&gic>;
284 local-mac-address = [06 00 00 00 00 01];
285 max-frame-size = <1518>;
286 tx-fifo-size = <32768>;
287 rx-fifo-size = <16384>;
294 #address-cells = <1>;
295 #size-cells = <0>;
297 resets = <&reset RSTMGR_TSN0_RSTLINE>;
298 compatible = "snps,dwcxgmac-mdio";
305 interrupt-parent = <&gic>;
308 local-mac-address = [06 00 00 00 00 02];
309 max-frame-size = <1518>;
310 tx-fifo-size = <32768>;
311 rx-fifo-size = <16384>;
318 #address-cells = <1>;
319 #size-cells = <0>;
321 resets = <&reset RSTMGR_TSN1_RSTLINE>;
322 compatible = "snps,dwcxgmac-mdio";
329 interrupt-parent = <&gic>;
332 local-mac-address = [06 00 00 00 00 03];
333 max-frame-size = <1518>;
334 tx-fifo-size = <32768>;
335 rx-fifo-size = <16384>;
342 #address-cells = <1>;
343 #size-cells = <0>;
345 resets = <&reset RSTMGR_TSN2_RSTLINE>;
346 compatible = "snps,dwcxgmac-mdio";