1/*
2 * Copyright (c) 2021 metraTec GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv6-m.dtsi>
8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <mem.h>
12#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
13
14/ {
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-m0+";
21			reg = <0>;
22		};
23	};
24
25	soc {
26		syscon: syscon@40000000 {
27			compatible = "nxp,lpc-syscon";
28			reg = <0x40000000 0x4000>;
29			#clock-cells = <1>;
30			reset: reset {
31				compatible = "nxp,lpc-syscon-reset";
32				#reset-cells = <1>;
33			};
34		};
35
36		sram0:memory@20000000 {
37			compatible = "mmio-sram";
38			reg = <0x20000000 DT_SIZE_K(64)>;
39		};
40
41		sramx:memory@4000000 {
42			compatible = "mmio-sram";
43			reg = <0x04000000 DT_SIZE_K(32)>;
44		};
45
46		flash0: flash@0 {
47			compatible = "soc-nv-flash";
48			reg = <0 DT_SIZE_K(256)>;
49		};
50
51		iocon: iocon@40001000 {
52			compatible = "nxp,lpc-iocon";
53			reg = <0x40001000 0x100>;
54			#address-cells = <1>;
55			#size-cells = <1>;
56			ranges = <0x0 0x40001000 0x100>;
57			pinctrl: pinctrl {
58				compatible = "nxp,lpc-iocon-pinctrl";
59			};
60		};
61
62		gpio: gpio@4008c000 {
63			compatible = "nxp,lpc-gpio";
64			reg = <0x4008c000 0x2484>;
65			#address-cells = <1>;
66			#size-cells = <0>;
67
68			gpio0: gpio@0 {
69				compatible = "nxp,lpc-gpio-port";
70				int-source = "pint";
71				gpio-controller;
72				#gpio-cells = <2>;
73				reg = <0>;
74			};
75
76			gpio1: gpio@1 {
77				compatible = "nxp,lpc-gpio-port";
78				int-source = "pint";
79				gpio-controller;
80				#gpio-cells = <2>;
81				reg = <1>;
82			};
83		};
84
85		pint: pint@40004000 {
86			compatible = "nxp,pint";
87			reg = <0x40004000 0x1000>;
88			interrupt-controller;
89			#interrupt-cells = <1>;
90			#address-cells = <0>;
91			interrupts = <4 2>, <5 2>, <6 2>, <7 2>;
92			num-lines = <4>;
93			num-inputs = <64>;
94		};
95
96		flexcomm0: flexcomm@40086000 {
97			compatible = "nxp,lpc-flexcomm";
98			reg = <0x40086000 0x1000>;
99			interrupts = <14 0>;
100			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
101			resets = <&reset NXP_SYSCON_RESET(1, 11)>;
102			status = "disabled";
103		};
104
105		flexcomm1: flexcomm@40087000 {
106			compatible = "nxp,lpc-flexcomm";
107			reg = <0x40087000 0x1000>;
108			interrupts = <15 0>;
109			clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
110			resets = <&reset NXP_SYSCON_RESET(1, 12)>;
111			status = "disabled";
112		};
113
114		flexcomm2: flexcomm@40088000 {
115			compatible = "nxp,lpc-flexcomm";
116			reg = <0x40088000 0x1000>;
117			interrupts = <16 0>;
118			clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
119			resets = <&reset NXP_SYSCON_RESET(1, 13)>;
120			status = "disabled";
121		};
122
123		flexcomm3: flexcomm@40089000 {
124			compatible = "nxp,lpc-flexcomm";
125			reg = <0x40089000 0x1000>;
126			interrupts = <17 0>;
127			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
128			resets = <&reset NXP_SYSCON_RESET(1, 14)>;
129			status = "disabled";
130		};
131
132		flexcomm4: flexcomm@4008a000 {
133			compatible = "nxp,lpc-flexcomm";
134			reg = <0x4008a000 0x1000>;
135			interrupts = <18 0>;
136			clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
137			resets = <&reset NXP_SYSCON_RESET(1, 15)>;
138			status = "disabled";
139		};
140
141		flexcomm5: flexcomm@40096000 {
142			compatible = "nxp,lpc-flexcomm";
143			reg = <0x40096000 0x1000>;
144			interrupts = <19 0>;
145			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
146			resets = <&reset NXP_SYSCON_RESET(1, 16)>;
147			status = "disabled";
148		};
149
150		flexcomm6: flexcomm@40097000 {
151			compatible = "nxp,lpc-flexcomm";
152			reg = <0x40097000 0x1000>;
153			interrupts = <20 0>;
154			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
155			resets = <&reset NXP_SYSCON_RESET(1, 17)>;
156			status = "disabled";
157		};
158
159		flexcomm7: flexcomm@40098000 {
160			compatible = "nxp,lpc-flexcomm";
161			reg = <0x40098000 0x1000>;
162			interrupts = <21 0>;
163			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
164			resets = <&reset NXP_SYSCON_RESET(1, 18)>;
165			status = "disabled";
166		};
167
168		sc_timer: pwm@40085000 {
169			compatible = "nxp,sctimer-pwm";
170			reg = <0x40085000 0x1000>;
171			status = "disabled";
172			interrupts = <12 0>;
173			clocks = <&syscon MCUX_SCTIMER_CLK>;
174			prescaler = <1>;
175			#pwm-cells = <3>;
176		};
177	};
178};
179
180&nvic {
181	arm,num-irq-priority-bits = <2>;
182};
183