Lines Matching +full:reset +full:- +full:cells
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
16 gpio-0 = &gpio0;
17 gpio-1 = &gpio1;
18 mailbox-0 = &mailbox0;
22 zephyr,flash-controller = &iap;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-m4f";
35 compatible = "arm,cortex-m0+";
42 compatible = "nxp,lpc-syscon";
44 #clock-cells = <1>;
45 reset: reset { label
46 compatible = "nxp,lpc-syscon-reset";
47 #reset-cells = <1>;
57 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000
60 * SRAM0-SRAM3 will be contiguous memory when present.
63 * to allocate memory to the different cores of the dual-core platforms.
66 compatible = "mmio-sram";
71 compatible = "zephyr,memory-region", "mmio-sram";
73 zephyr,memory-region = "SRAM1";
77 compatible = "zephyr,memory-region", "mmio-sram";
79 zephyr,memory-region = "SRAM2";
88 compatible = "mmio-sram";
92 iap: flash-controller@4009c000 {
93 compatible = "nxp,iap-fmc54";
95 #address-cells = <1>;
96 #size-cells = <1>;
99 compatible = "soc-nv-flash";
101 erase-block-size = <256>;
102 write-block-size = <256>;
107 compatible = "nxp,lpc-iocon";
109 #address-cells = <1>;
110 #size-cells = <1>;
113 compatible = "nxp,lpc-iocon-pinctrl";
118 compatible = "nxp,lpc-gpio";
120 #address-cells = <1>;
121 #size-cells = <0>;
124 compatible = "nxp,lpc-gpio-port";
126 int-source = "pint";
127 gpio-controller;
128 #gpio-cells = <2>;
132 compatible = "nxp,lpc-gpio-port";
134 int-source = "pint";
135 gpio-controller;
136 #gpio-cells = <2>;
143 interrupt-controller;
144 #interrupt-cells = <1>;
145 #address-cells = <0>;
148 num-lines = <8>;
149 num-inputs = <64>;
153 compatible = "nxp,lpc-mailbox";
160 compatible = "nxp,lpc-flexcomm";
164 resets = <&reset NXP_SYSCON_RESET(1, 11)>;
169 compatible = "nxp,lpc-flexcomm";
173 resets = <&reset NXP_SYSCON_RESET(1, 12)>;
178 compatible = "nxp,lpc-flexcomm";
182 resets = <&reset NXP_SYSCON_RESET(1, 13)>;
187 compatible = "nxp,lpc-flexcomm";
191 resets = <&reset NXP_SYSCON_RESET(1, 14)>;
196 compatible = "nxp,lpc-flexcomm";
200 resets = <&reset NXP_SYSCON_RESET(1, 15)>;
205 compatible = "nxp,lpc-flexcomm";
209 resets = <&reset NXP_SYSCON_RESET(1, 16)>;
214 compatible = "nxp,lpc-flexcomm";
218 resets = <&reset NXP_SYSCON_RESET(1, 17)>;
223 compatible = "nxp,lpc-flexcomm";
227 resets = <&reset NXP_SYSCON_RESET(1, 18)>;
234 arm,num-irq-priority-bits = <3>;