1# Copyright (c) 2022, Google Inc
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Reset and Clock Control (RCC) node.
6  This node is in charge of reset control for AHB (Advanced High Performance)
7  and APB (Advanced Peripheral) bus domains.
8
9  To specify the reset line in a peripheral, the standard resets property needs
10  to be used, e.g.:
11
12    usart1: serial@xxx {
13        ...
14        /* Cell contains information about RCU register offset and bit */
15        resets = <&rctl STM32_RESET(ABP2, 4U)>;
16        ...
17    };
18
19  RCC reset cells are available in
20  include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
21
22compatible: "st,stm32-rcc-rctl"
23
24include: [reset-controller.yaml, base.yaml]
25
26properties:
27  "#reset-cells":
28    const: 1
29
30  set-bit-to-deassert:
31    type: boolean
32    description: |
33      Indicates if the driver should set bit in clear register to
34      deassert reset.
35
36reset-cells:
37  - id
38