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/Zephyr-latest/dts/arm/nxp/
Dnxp_s32k146.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/clock/nxp_s32k146_clock.h>
12 cpu@0 {
13 compatible = "arm,cortex-m4f";
20 * and burst accesses cannot occur across the 0x20000000 boundary
25 compatible = "mmio-sram";
26 reg = <0x1fff0000 DT_SIZE_K(64)>;
30 compatible = "mmio-sram";
31 reg = <0x20000000 DT_SIZE_K(60)>;
36 /delete-node/ &lpi2c1;
[all …]
Dnxp_k66.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 reg = <0x00000000 DT_SIZE_M(2)>;
18 reg = <0x400c4000 0x14>;
19 interrupts = <86 0>;
20 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>;
22 dma-names = "rx", "tx";
28 reg = <0x400a4000 0x1000>;
29 interrupts = <94 0>, <95 0>, <96 0>, <97 0>, <98 0>, <99 0>;
30 interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning",
31 "rx-warning", "wake-up";
[all …]
/Zephyr-latest/include/zephyr/net/
Dmii.h5 * SPDX-License-Identifier: Apache-2.0
19 * @version 0.8.0
26 #define MII_BMCR 0x0
28 #define MII_BMSR 0x1
30 #define MII_PHYID1R 0x2
32 #define MII_PHYID2R 0x3
33 /** Auto-Negotiation Advertisement Register */
34 #define MII_ANAR 0x4
35 /** Auto-Negotiation Link Partner Ability Reg */
36 #define MII_ANLPAR 0x5
[all …]
/Zephyr-latest/samples/subsys/debug/fuzz/
DREADME.rst1 .. zephyr:code-sample:: fuzzing
21 .. code-block:: console
23 $ clang --version
25 Target: x86_64-pc-linux-gnu
29 $ west build -t run -b native_sim/native/64 samples/subsys/debug/fuzz
31 Over 10-20 seconds or so (runtimes can be quite variable) you will see
38 .. code-block:: console
40 -- west build: running target run
41 [0/1] cd /home/andy/z/zephyr/build && .../andy/z/zephyr/build/zephyr/zephyr.exe
42 INFO: Running with entropic power schedule (0xFF, 100).
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/Zephyr-latest/dts/bindings/can/
Dnxp,flexcan.yaml2 # SPDX-License-Identifier: Apache-2.0
11 reg = <0x40024000 0x1000>;
12 interrupts = <78 0>, <79 0>, <80 0>, <81 0>;
13 interrupt-names = "warning", "error", "wake-up", "mb-0-15";
15 clk-source = <1>;
16 pinctrl-0 = <&pinmux_flexcan0>;
17 pinctrl-names = "default";
19 can-transceiver {
20 max-bitrate = <1000000>;
26 include: ["can-controller.yaml", "pinctrl-device.yaml"]
[all …]
/Zephyr-latest/boards/wiznet/w5500_evb_pico/
Dw5500_evb_pico.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
13 #include "w5500_evb_pico-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #include <zephyr/dt-bindings/i2c/i2c.h>
22 zephyr,flash-controller = &ssi;
24 zephyr,shell-uart = &uart0;
25 zephyr,code-partition = &code_partition;
29 compatible = "raspberrypi,pico-header";
30 #gpio-cells = <2>;
[all …]
/Zephyr-latest/arch/x86/include/
Dkernel_arch_data.h3 * SPDX-License-Identifier: Apache-2.0
14 #define IV_DIVIDE_ERROR 0
29 #define IV_RESERVED 15
41 * EFLAGS/RFLAGS definitions. (RFLAGS is just zero-extended EFLAGS.)
56 #define CR4_PSE BIT(4) /* Page size extension (4MB pages) */
/Zephyr-latest/boards/nxp/rd_rw612_bga/
Drd_rw612_bga.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include "rd_rw612_bga-pinctrl.dtsi"
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
16 usart-0 = &flexcomm3;
18 i2c-0 = &flexcomm2;
20 dmic-dev = &dmic0;
21 mcuboot-button0 = &sw_4;
22 pwm-0 = &sctimer;
28 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-latest/boards/arm/mps2/doc/
Dmps2_an521.rst10 on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
31 for use with QEMU and unit tests for the ARM Cortex-M33.
37 The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores
40 both Secure and Non-Secure firmware images may be built.
44 +----------------------+-------------------------------------------------------+
47 | mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 |
[all …]
Dmps2_an385.rst10 the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit UART
39 - ARM Cortex-M3 (AN385)
40 - ARM IoT Subsystem for Cortex-M
41 - Form factor: 140x120cm
42 - ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
43 - Video: QSVGA touch screen panel, 4bit RGB VGA connector
44 - Audio: Audio Codec
[all …]
/Zephyr-latest/boards/raspberrypi/rpi_pico2/
Drpi_pico2.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include "rpi_pico2-pinctrl.dtsi"
13 #include "../common/rpi_pico-led.dtsi"
20 zephyr,shell-uart = &uart0;
21 zephyr,code-partition = &code_partition;
29 compatible = "raspberrypi,pico-header";
30 #gpio-cells = <2>;
31 gpio-map-mask = <0xffffffff 0xffffffc0>;
[all …]
/Zephyr-latest/boards/raspberrypi/rpi_pico/
Drpi_pico-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include "rpi_pico-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
20 zephyr,flash-controller = &ssi;
22 zephyr,shell-uart = &uart0;
23 zephyr,code-partition = &code_partition;
32 compatible = "raspberrypi,pico-header";
33 #gpio-cells = <2>;
34 gpio-map-mask = <0xffffffff 0xffffffc0>;
[all …]
/Zephyr-latest/drivers/dma/
Ddma_pl330.h4 * SPDX-License-Identifier: Apache-2.0
35 #define MAX_BURST_LEN 0xf /* 16byte data */
42 #define PL330_MAX_OFFSET 0x100000000
44 /* PL330 supports max 16MB dma based on AXI bus size */
45 #define PL330_MAX_DMA_SIZE 0x1000000
48 #define PL330_LOOP_COUNTER0_MAX 0x100
49 #define PL330_LOOP_COUNTER1_MAX 0x100
51 #define MAX_DMA_CHANNELS DT_INST_PROP(0, dma_channels)
53 #define DMAC_PL330_CS0 0x100
54 #define DMAC_PL330_DBGSTATUS 0xd00
[all …]
/Zephyr-latest/boards/ezurio/mg100/
Dmg100.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "mg100-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
24 zephyr,code-partition = &slot0_partition;
29 compatible = "gpio-leds";
45 compatible = "gpio-keys";
[all …]
/Zephyr-latest/subsys/modbus/
Dmodbus_internal.h5 * SPDX-License-Identifier: Apache-2.0
9 * Parts of this file are based on mb.h from uC/Modbus Stack.
14 * Copyright 2003-2020 Silicon Laboratories Inc. www.silabs.com
16 * SPDX-License-Identifier: APACHE-2.0
20 * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
46 #define MODBUS_FC15_COILS_WR 15
49 /* Diagnostic sub-function codes */
50 #define MODBUS_FC08_SUBF_QUERY 0
56 #define MODBUS_FC08_SUBF_SERVER_NO_RESP_CTR 15
59 #define MODBUS_COIL_OFF_CODE 0x0000
[all …]
/Zephyr-latest/scripts/kconfig/
Dkconfigfunctions.py1 # Copyright (c) 2018-2019 Linaro
4 # SPDX-License-Identifier: Apache-2.0
16 sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts", "dts",
17 "python-devicetree", "src"))
43 return 0
52 if unit in {'mb', 'Mb'}:
157 foo: some-node { ... };
169 return 0
172 return 0
175 return 0
[all …]
/Zephyr-latest/boards/ezurio/pinnacle_100_dvk/
Dpinnacle_100_dvk.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
10 #include "pinnacle_100_dvk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "ezurio,pinnacle-100-dvk";
19 zephyr,shell-uart = &uart0;
20 zephyr,uart-mcumgr = &uart0;
21 zephyr,bt-mon-uart = &uart0;
24 zephyr,code-partition = &slot0_partition;
29 compatible = "gpio-leds";
[all …]
/Zephyr-latest/boards/beagle/beaglebone_ai64/doc/
Dindex.rst6 BeagleBone AI-64 is a computational platform powered by TI J721E SoC, which is
12 BeagleBone AI-64 is powered by TI J721E SoC, which has three domains (MAIN,
17 ----------------
24 --------------------------
27 32-bit input address into a 48-bit output address. Any input transaction that
32 ------------------------
36 a level or a pulse (both active-high). The VIM has two interrupt outputs per core
44 +-----------+------------+-----------------------+
47 | UART | on-chip | serial port-polling |
48 | | | serial port-interrupt |
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
36 [7:0] should reflect the density value itself and [15:8] should reflect
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
[all …]
/Zephyr-latest/boards/arm/v2m_musca_b1/doc/
Dindex.rst10 on the V2M Musca B1 board. It provides support for the Musca B1 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
31 - ARM Cortex-M33
32 - ARM IoT Subsystem for Cortex-M33
33 - Memory
35 - 512KB on-chip system memory SRAM.
36 - 8MB of external QSPI flash.
[all …]
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
31 dmic-dev = &dmic0;
32 mcuboot-button0 = &user_button_1;
[all …]
/Zephyr-latest/drivers/sensor/bosch/bmp180/
Dbmp180.c5 * SPDX-License-Identifier: Apache-2.0
8 * https://www.mouser.hk/datasheet/2/783/BST-BMP180-DS000-1509579.pdf
45 int16_t mb; member
64 const struct bmp180_config *cfg = dev->config; in bmp180_bus_check()
66 return i2c_is_ready_dt(&cfg->i2c) ? 0 : -ENODEV; in bmp180_bus_check()
72 const struct bmp180_config *cfg = dev->config; in bmp180_reg_read()
74 return i2c_burst_read_dt(&cfg->i2c, start, buf, size); in bmp180_reg_read()
80 const struct bmp180_config *cfg = dev->config; in bmp180_reg_write()
82 return i2c_reg_write_byte_dt(&cfg->i2c, reg, val); in bmp180_reg_write()
89 struct bmp180_data *data = dev->data; in bmp180_attr_set_oversampling()
[all …]
/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor_ll.c4 * SPDX-License-Identifier: Apache-2.0
20 return -EINVAL; in cad_qspi_idle()
23 return (sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_IDLE) >> 31; in cad_qspi_idle()
30 return -EINVAL; in cad_qspi_set_baudrate_div()
33 if (div > 0xf) { in cad_qspi_set_baudrate_div()
37 sys_clear_bits(cad_params->reg_base + CAD_QSPI_CFG, ~CAD_QSPI_CFG_BAUDDIV_MSK); in cad_qspi_set_baudrate_div()
39 sys_set_bits(cad_params->reg_base + CAD_QSPI_CFG, CAD_QSPI_CFG_BAUDDIV(div)); in cad_qspi_set_baudrate_div()
41 return 0; in cad_qspi_set_baudrate_div()
49 return -EINVAL; in cad_qspi_configure_dev_size()
55 cad_params->reg_base + CAD_QSPI_DEVSZ); in cad_qspi_configure_dev_size()
[all …]
/Zephyr-latest/boards/st/steval_stwinbx1/
Dsteval_stwinbx1.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics STEVAL-STWINBX1 Development kit";
19 zephyr,code-partition = &slot0_partition;
21 zephyr,bt-hci = &hci_spi;
25 compatible = "gpio-leds";
37 compatible = "pwm-leds";
41 label = "LED_1 - PWM5";
[all …]
/Zephyr-latest/boards/arm/v2m_musca_s1/doc/
Dindex.rst3 ARM V2M Musca-S1
10 on the V2M Musca-S1 board. It provides support for the Musca-S1 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
20 :alt: ARM V2M Musca-S1
22 More information about the board can be found at the `V2M Musca-S1 Website`_.
27 ARM V2M MUSCA-S1 provides the following hardware components:
29 - ARM Cortex-M33 (with FPU and DSP)
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