Lines Matching +full:mb +full:- +full:0 +full:- +full:15
10 on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
31 for use with QEMU and unit tests for the ARM Cortex-M33.
37 The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores
40 both Secure and Non-Secure firmware images may be built.
44 +----------------------+-------------------------------------------------------+
47 | mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 |
48 +----------------------+-------------------------------------------------------+
49 | mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 |
50 +----------------------+-------------------------------------------------------+
52 +----------------------+-------------------------------------------------------+
57 The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory
59 non-secure regions, where the secure memory alias has an offset of
60 0x10000000 relative to non-secure.
63 the offset value is the offset from the base of the 4MB code or SRAM block,
66 +-------------------------+-----+----------------+----------------+------------+
69 | mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S |
70 +-------------------------+-----+----------------+----------------+------------+
71 | mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS |
72 +-------------------------+-----+----------------+----------------+------------+
73 | mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS |
74 +-------------------------+-----+----------------+----------------+------------+
76 The ``mps2/an521/cpu0/ns`` board target is intended to be used with TF-M, with the
77 Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M
79 non-secure processing environment. The non-secure Zephyr image is offset to
80 make room for the secure bootloader, and the secure firmware (TF-M), resulting
81 in a starting address of 0x00100000. SRAM begins with a 1MB offset at
82 0x28100000.
85 AN521, using the final 468KB code memory in the 4MB code block. This value
86 is chosen to maintain compatibility with TF-M, which marks that final 468KB
88 3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB
89 (address 0x28180000).
93 the second core to the worst-case scenario from TF-M.
105 - Dual core ARM Cortex-M33
106 - Soft Macro Model (SMM) implementation of SSE-200 subsystem
107 - Memory
109 - 4MB of code memory (SSRAM1)
110 - 4MB of SRAM (SSRAM2 and SSRAM3)
111 - 16MB of parallel SRAM (PSRAM, non-secure only)
112 - 8KB of NVM code
114 - Debug
116 - P-JTAG, SWD & 16-bit TRACE
117 - UART port
119 - Interface
121 - AHB GPIO connected to the EXP port
122 - UART
123 - SPI
124 - I2C
125 - I2S
126 - Color LCD serial interface
127 - Ethernet
128 - VGA
130 - On-board Peripherals
132 - Color LCD
133 - 8 LEDs
134 - 8 Switches
135 - External SSRAM1, SSRAM2 & SSRAM3
136 - SMSC9220
137 - CS42L52
145 - ON power on
146 - nSRST: Cortex-M33 system reset and CoreSight debug reset
147 - USERPB0 and USERPB1: User defined buttons
155 +-----------+------------+-------------------------------------+
158 | NVIC | on-chip | nested vector interrupt controller |
159 +-----------+------------+-------------------------------------+
160 | SYSTICK | on-chip | systick |
161 +-----------+------------+-------------------------------------+
162 | UART | on-chip | serial port-polling; |
163 | | | serial port-interrupt |
164 +-----------+------------+-------------------------------------+
165 | PINMUX | on-chip | pinmux |
166 +-----------+------------+-------------------------------------+
167 | GPIO | on-chip | gpio |
168 +-----------+------------+-------------------------------------+
169 | WATCHDOG | on-chip | watchdog |
170 +-----------+------------+-------------------------------------+
171 | TIMER | on-chip | timer |
172 +-----------+------------+-------------------------------------+
184 MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
186 A Cortex-M33-based board uses vectored exceptions. This means each exception
189 Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed
192 +------+------------+----------------+--------------------------+
196 +------+------------+----------------+--------------------------+
198 +------+------------+----------------+--------------------------+
200 +------+------------+----------------+--------------------------+
202 +------+------------+----------------+--------------------------+
204 +------+------------+----------------+--------------------------+
210 +------+------------+----------------+--------------------------+
215 +------+------------+----------------+--------------------------+
217 +------+------------+----------------+--------------------------+
219 +------+------------+----------------+--------------------------+
221 +------+------------+----------------+--------------------------+
223 | | | | run-time exceptions, |
225 +------+------------+----------------+--------------------------+
228 +------+------------+----------------+--------------------------+
230 +------+------------+----------------+--------------------------+
232 +------+------------+----------------+--------------------------+
233 | 15 | SYSTICK | | system clock |
234 +------+------------+----------------+--------------------------+
236 +------+------------+----------------+--------------------------+
238 +------+------------+----------------+--------------------------+
240 +------+------------+----------------+--------------------------+
246 bits of IO. These controllers are responsible for pin-muxing, input/output,
247 pull-up, etc.
251 - Pins 0 - 15 are for GPIO0
252 - Pins 16 - 31 are for GPIO1
253 - Pins 32 - 47 are for GPIO2
254 - Pins 48 - 51 are for GPIO3
258 .. rst-class:: rst-columns
260 - D0 : EXT_0
261 - D1 : EXT_4
262 - D2 : EXT_2
263 - D3 : EXT_3
264 - D4 : EXT_1
265 - D5 : EXT_6
266 - D6 : EXT_7
267 - D7 : EXT_8
268 - D8 : EXT_9
269 - D9 : EXT_10
270 - D10 : EXT_12
271 - D11 : EXT_13
272 - D12 : EXT_14
273 - D13 : EXT_11
274 - D14 : EXT_15
275 - D15 : EXT_5
276 - D16 : EXT_16
277 - D17 : EXT_17
278 - D18 : EXT_18
279 - D19 : EXT_19
280 - D20 : EXT_20
281 - D21 : EXT_21
282 - D22 : EXT_22
283 - D23 : EXT_23
284 - D24 : EXT_24
285 - D25 : EXT_25
286 - D26 : EXT_26
287 - D27 : EXT_30
288 - D28 : EXT_28
289 - D29 : EXT_29
290 - D30 : EXT_27
291 - D31 : EXT_32
292 - D32 : EXT_33
293 - D33 : EXT_34
294 - D34 : EXT_35
295 - D35 : EXT_36
296 - D36 : EXT_38
297 - D37 : EXT_39
298 - D38 : EXT_40
299 - D39 : EXT_44
300 - D40 : EXT_41
301 - D41 : EXT_31
302 - D42 : EXT_37
303 - D43 : EXT_42
304 - D44 : EXT_43
305 - D45 : EXT_45
306 - D46 : EXT_46
307 - D47 : EXT_47
308 - D48 : EXT_48
309 - D49 : EXT_49
310 - D50 : EXT_50
311 - D51 : EXT_51
315 .. rst-class:: rst-columns
317 - UART_3_RX : D0
318 - UART_3_TX : D1
319 - SPI_3_CS : D10
320 - SPI_3_MOSI : D11
321 - SPI_3_MISO : D12
322 - SPI_3_SCLK : D13
323 - I2C_3_SDA : D14
324 - I2C_3_SCL : D15
325 - UART_4_RX : D26
326 - UART_4_TX : D30
327 - SPI_4_CS : D36
328 - SPI_4_MOSI : D37
329 - SPI_4_MISO : D38
330 - SPI_4_SCK : D39
331 - I2C_4_SDA : D40
332 - I2C_4_SCL : D41
339 MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC).
341 .. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON.
348 .. rst-class:: rst-columns
350 - MAINCLK : 20MHz
351 - SYSCLK : 20MHz
352 - S32KCLK : 32kHz
353 - TRACECLK : 20MHz
354 - SWCLKTCK : 20MHz
355 - TRACECLKIN : 20MHz
363 UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports.
368 - Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define
369 secure and non-secure memory maps. By default, all of the memory space is
371 - Secure and Non-secure peripherals via the Peripheral Protection Controller
372 (PPC). Peripherals can be assigned as secure or non-secure accessible
373 - Secure boot
374 - Secure `AMBA®`_ interconnect
381 reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and
393 Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
396 Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure
398 or `Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built
404 using TF-M.
406 Building the Secure firmware with TF-M
407 --------------------------------------
409 The process to build the Secure firmware image using TF-M and the Non-Secure
412 1. Build the Non-Secure Zephyr application
413 for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``.
414 To invoke the building of TF-M the Zephyr build system requires the
416 default when building Zephyr as a Non-Secure application.
419 * Build the Non-Secure firmware image as a regular Zephyr application
420 * Build a TF-M (secure) firmware image
426 Depending on the TF-M configuration, an application DTS overlay may be
427 required, to adjust the Non-Secure image Flash and SRAM starting address
431 -----------------------------------------
433 The process to build the Secure and the Non-Secure firmware images
437 using ``-DBOARD=mps2/an521`` and
440 2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0)
441 using ``-DBOARD=mps2/an521/cpu0/ns``.
448 and :ref:`application_run`), using ``-DBOARD=mps2/an521`` for
451 When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0),
453 Non-Secure access to all CPU resources utilized by the Non-Secure application
455 Non-Secure application.
460 - AHB5 TrustZone Memory Protection Controller (MPC)
461 - AHB5 TrustZone Peripheral Protection Controller (PPC)
462 - Implementation-Defined Attribution Unit (IDAU)
464 For more details refer to `Corelink SSE-200 Subsystem`_.
471 Applications may be built for the second Cortex-M33
475 and :ref:`application_run`), using ``-DBOARD=mps2/an521/cpu1`` for
479 secure-only firmware for CPU0, which will be used to boot the remote
488 - A USB connection to the host computer, which exposes a Mass Storage
489 - A Serial Port which is J10 on MPS2+ board
492 Here is an example for the :zephyr:code-sample:`hello_world` application built as
493 a secure-only application for CPU0.
495 .. zephyr-app-commands::
496 :zephyr-app: samples/hello_world
503 - Speed: 115200
504 - Data: 8 bits
505 - Parity: None
506 - Stop bits: 1
511 .. code-block:: console
517 ---------------------------------------
520 the board boots up, using files stored on the on-board Micro SD card. The
530 2. Open ``<MPS2 device name>/MB/HBI0263C/AN521/images.txt``.
533 .. code-block:: bash
540 IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program
548 .. code-block:: console
552 .. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and mult…
556 https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2
565 https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html
567 .. _Corelink SSE-200 Subsystem:
568 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200
571 https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU-
574 https://developer.arm.com/products/architecture/system-architectures/amba