Lines Matching +full:mb +full:- +full:0 +full:- +full:15
5 * SPDX-License-Identifier: Apache-2.0
19 * @version 0.8.0
26 #define MII_BMCR 0x0
28 #define MII_BMSR 0x1
30 #define MII_PHYID1R 0x2
32 #define MII_PHYID2R 0x3
33 /** Auto-Negotiation Advertisement Register */
34 #define MII_ANAR 0x4
35 /** Auto-Negotiation Link Partner Ability Reg */
36 #define MII_ANLPAR 0x5
37 /** Auto-Negotiation Expansion Register */
38 #define MII_ANER 0x6
39 /** Auto-Negotiation Next Page Transmit Register */
40 #define MII_ANNPTR 0x7
41 /** Auto-Negotiation Link Partner Received Next Page Reg */
42 #define MII_ANLPRNPR 0x8
43 /** 1000BASE-T Control Register */
44 #define MII_1KTCR 0x9
45 /** 1000BASE-T Status Register */
46 #define MII_1KSTSR 0xa
48 #define MII_MMD_ACR 0xd
50 #define MII_MMD_AADR 0xe
52 #define MII_ESTAT 0xf
56 #define MII_BMCR_RESET (1 << 15)
61 /** Auto-Negotiation enable */
67 /** restart auto-negotiation */
75 /** select speed 10 Mb/s */
76 #define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13)
77 /** select speed 100 Mb/s */
78 #define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13)
79 /** select speed 1000 Mb/s */
80 #define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13)
83 /** 100BASE-T4 capable */
84 #define MII_BMSR_100BASE_T4 (1 << 15)
85 /** 100BASE-X full duplex capable */
87 /** 100BASE-X half duplex capable */
89 /** 10 Mb/s full duplex capable */
91 /** 10 Mb/s half duplex capable */
93 /** 100BASE-T2 full duplex capable */
95 /** 100BASE-T2 half duplex capable */
97 /** extend status information in reg 15 */
101 /** Auto-negotiation process completed */
105 /** PHY is able to perform Auto-Negotiation */
112 #define MII_BMSR_EXTEND_CAPAB (1 << 0)
114 /* Auto-negotiation Advertisement Register (ANAR) bit definitions */
115 /* Auto-negotiation Link Partner Ability Register (ANLPAR) bit definitions */
117 #define MII_ADVERTISE_NEXT_PAGE (1 << 15)
126 /** try for 100BASE-T4 support */
128 /** try for 100BASE-X full duplex support */
130 /** try for 100BASE-X support */
132 /** try for 10 Mb/s full duplex support */
134 /** try for 10 Mb/s half duplex support */
137 #define MII_ADVERTISE_SEL_MASK (0x1F << 0)
139 #define MII_ADVERTISE_SEL_IEEE_802_3 0x01
141 /* 1000BASE-T Control Register bit definitions */
142 /** try for 1000BASE-T full duplex support */
144 /** try for 1000BASE-T half duplex support */
153 /** 1000BASE-X full-duplex capable */
154 #define MII_ESTAT_1000BASE_X_FULL (1 << 15)
155 /** 1000BASE-X half-duplex capable */
157 /** 1000BASE-T full-duplex capable */
159 /** 1000BASE-T half-duplex capable */
164 #define MII_MMD_ACR_DEVAD_MASK (0x1F << 0)
166 #define MII_MMD_ACR_ADDR (0x00 << 14)
167 #define MII_MMD_ACR_DATA_NO_POS_INC (0x01 << 14)
168 #define MII_MMD_ACR_DATA_RW_POS_INC (0x10 << 14)
169 #define MII_MMD_ACR_DATA_W_POS_INC (0x11 << 14)