1.. _v2m_musca_b1_board: 2 3ARM V2M Musca B1 4################ 5 6Overview 7******** 8 9The v2m_musca_b1 board configuration is used by Zephyr applications that run 10on the V2M Musca B1 board. It provides support for the Musca B1 ARM Cortex-M33 11CPU and the following devices: 12 13- Nested Vectored Interrupt Controller (NVIC) 14- System Tick System Clock (SYSTICK) 15- Cortex-M System Design Kit GPIO 16- Cortex-M System Design Kit UART 17 18.. image:: img/v2m_musca_b1.jpg 19 :align: center 20 :alt: ARM V2M Musca B1 21 22More information about the board can be found at the `V2M Musca B1 Website`_. 23 24Hardware 25******** 26 27ARM V2M MUSCA B1 provides the following hardware components: 28 29 30 31- ARM Cortex-M33 32- ARM IoT Subsystem for Cortex-M33 33- Memory 34 35 - 512KB on-chip system memory SRAM. 36 - 8MB of external QSPI flash. 37 - 4MB on-chip boot eFlash. 38 39- Debug 40 41 - JTAG, SWD & 4 bit TRACE. 42 - DAPLink with a virtual UART port. 43 44- Arduino interface 45 46 - 16 3V3 GPIO. 47 - UART. 48 - SPI. 49 - I2C. 50 - I2S. 51 - 3-channel PWM. 52 - 6-channel analog interface. 53 54- On-board Peripherals 55 56 - User RGB LED. 57 - Gyro sensor. 58 - Combined ADC/DAC/temperature sensor. 59 - Secure Digital I/O (SDIO) microSD card. 60 61 62User push buttons 63================= 64 65The v2m_musca_b1 board provides the following user push buttons: 66 67- PBON power on/off. 68- nSRST: Cortex-M33 system reset and CoreSight debug reset. 69- ISP: Updates DAPLink firmware. 70 71 72Supported Features 73=================== 74 75The v2m_musca_b1 board configuration supports the following hardware features: 76 77+-----------+------------+-------------------------------------+ 78| Interface | Controller | Driver/Component | 79+===========+============+=====================================+ 80| NVIC | on-chip | nested vector interrupt controller | 81+-----------+------------+-------------------------------------+ 82| SYSTICK | on-chip | systick | 83+-----------+------------+-------------------------------------+ 84| UART | on-chip | serial port-polling; | 85| | | serial port-interrupt | 86+-----------+------------+-------------------------------------+ 87| PINMUX | on-chip | pinmux | 88+-----------+------------+-------------------------------------+ 89| GPIO | on-chip | gpio | 90+-----------+------------+-------------------------------------+ 91| WATCHDOG | on-chip | watchdog | 92+-----------+------------+-------------------------------------+ 93| TIMER | on-chip | timer | 94+-----------+------------+-------------------------------------+ 95 96Other hardware features are not currently supported by the port. 97See the `V2M Musca B1 Website`_ for a complete list of V2M Musca board hardware 98features. 99 100The default configuration can be found in the defconfig file: 101:zephyr_file:`boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig`. 102 103Interrupt Controller 104==================== 105 106Musca B1 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. 107 108A Cortex-M33-based board uses vectored exceptions. This means each exception 109calls a handler directly from the vector table. 110 111Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed 112in the following table: 113 114+------+------------+----------------+--------------------------+ 115| Exc# | Name | Remarks | Used by Zephyr Kernel | 116+======+============+================+==========================+ 117| 1 | Reset | | system initialization | 118+------+------------+----------------+--------------------------+ 119| 2 | NMI | | system fatal error | 120+------+------------+----------------+--------------------------+ 121| 3 | Hard fault | | system fatal error | 122+------+------------+----------------+--------------------------+ 123| 4 | MemManage | MPU fault | system fatal error | 124+------+------------+----------------+--------------------------+ 125| 5 | Bus | | system fatal error | 126+------+------------+----------------+--------------------------+ 127| 6 | Usage | Undefined | system fatal error | 128| | fault | instruction, | | 129| | | or switch | | 130| | | attempt to ARM | | 131| | | mode | | 132+------+------------+----------------+--------------------------+ 133| 7 | SecureFault| Unauthorized | system fatal error | 134| | | access to | | 135| | | secure region | | 136| | | from ns space | | 137+------+------------+----------------+--------------------------+ 138| 8 | Reserved | | not handled | 139+------+------------+----------------+--------------------------+ 140| 9 | Reserved | | not handled | 141+------+------------+----------------+--------------------------+ 142| 10 | Reserved | | not handled | 143+------+------------+----------------+--------------------------+ 144| 11 | SVC | | system calls, kernel | 145| | | | run-time exceptions, | 146| | | | and IRQ offloading | 147+------+------------+----------------+--------------------------+ 148| 12 | Debug | | system fatal error | 149| | monitor | | | 150+------+------------+----------------+--------------------------+ 151| 13 | Reserved | | not handled | 152+------+------------+----------------+--------------------------+ 153| 14 | PendSV | | context switch | 154+------+------------+----------------+--------------------------+ 155| 15 | SYSTICK | | system clock | 156+------+------------+----------------+--------------------------+ 157| 16 | Reserved | | not handled | 158+------+------------+----------------+--------------------------+ 159| 17 | Reserved | | not handled | 160+------+------------+----------------+--------------------------+ 161| 18 | Reserved | | not handled | 162+------+------------+----------------+--------------------------+ 163 164Pin Mapping 165=========== 166 167The ARM V2M Musca B1 Board has 4 GPIO controllers. These controllers are 168responsible for pin-muxing, input/output, pull-up, etc. 169 170All GPIO controller pins are exposed via the following sequence of pin numbers: 171 172- Pins 0 - 15 are for GPIO 173 174Mapping from the ARM V2M Musca B1 Board pins to GPIO controllers: 175 176.. rst-class:: rst-columns 177 178 - D0 : P0_0 179 - D1 : P0_1 180 - D2 : P0_2 181 - D3 : P0_3 182 - D4 : P0_4 183 - D5 : P0_5 184 - D6 : P0_6 185 - D7 : P0_7 186 - D8 : P0_8 187 - D9 : P0_9 188 - D10 : P0_10 189 - D11 : P0_11 190 - D12 : P0_12 191 - D13 : P0_13 192 - D14 : P0_14 193 - D15 : P0_15 194 195Peripheral Mapping: 196 197.. rst-class:: rst-columns 198 199 - UART_0_RX : D0 200 - UART_0_TX : D1 201 - SPI_0_CS : D10 202 - SPI_0_MOSI : D11 203 - SPI_0_MISO : D12 204 - SPI_0_SCLK : D13 205 - I2C_0_SDA : D14 206 - I2C_0_SCL : D15 207 208For more details please refer to `Musca B1 Technical Reference Manual (TRM)`_. 209 210 211RGB LED 212============ 213 214Musca B1 has a built-in RGB LED connected to GPIO[4:2] pins. 215 216- Red LED connected at GPIO[2] pin,with optional PWM0. 217- Green LED connected at GPIO[3] pin,with optional PWM1. 218- Blue LED connected at GPIO[4] pin,with optional PWM2. 219 220.. note:: The SCC registers select the functions of pins GPIO[4:2]. 221 222System Clock 223============ 224 225V2M Musca B1 has a 32.768kHz crystal clock. The clock goes to a PLL and is 226multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The 227default is 40MHz but can be increased to 160MHz maximum for the secondary 228processor (CPU1) via software configuration. The maximum clock frequency 229for the primary processor (CPU0) is 40MHz. 230 231Serial Port 232=========== 233 234The ARM Musca B1 processor has two UARTs. Both the UARTs have only two wires 235for RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, 236by default, uses UART1. 237 238Security components 239=================== 240 241- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define 242 secure and non-secure memory maps. By default, all of the memory space is 243 defined to be secure accessible only. 244- Secure and Non-secure peripherals via the Peripheral Protection Controller 245 (PPC). Peripherals can be assigned as secure or non-secure accessible. 246- Secure boot. 247- Secure `AMBA®`_ interconnect. 248 249Serial Configuration Controller (SCC) 250===================================== 251 252The ARM Musca B1 test chip implements a Serial Configuration Control (SCC) 253register. The purpose of this register is to allow individual control of 254clocks, reset-signals and interrupts to peripherals, and pin-muxing. 255 256Boot memory 257================ 258Normal Musca-B1 test chip boot operation is from 4MB eFlash by default, and 259it offers the fastest boot method. 260Musca-B1 test chip also support to boot from 8MB QSPI. You can update the 261DAPLink firmware for either QSPI or eFlash for booting. 262 263Programming and Debugging 264************************* 265 266Musca B1 supports the v8m security extension, and by default boots to the 267secure state. 268 269When building a secure/non-secure application, the secure application will 270have to set the idau/sau and mpc configuration to permit access from the 271non-secure application before jumping. 272 273The following system components are required to be properly configured during the 274secure firmware: 275 276- AHB5 TrustZone Memory Protection Controller (MPC). 277- AHB5 TrustZone Peripheral Protection Controller (PPC). 278- Implementation-Defined Attribution Unit (IDAU). 279 280For more details please refer to `Corelink SSE-200 Subsystem`_. 281 282Flashing 283======== 284 285DAPLink 286--------- 287 288V2M Musca B1 provides: 289 290- A USB connection to the host computer, which exposes a Mass Storage and an 291 USB Serial Port. 292- A Serial Flash device, which implements the USB flash disk file storage. 293- A physical UART connection which is relayed over interface USB Serial port. 294 295This interfaces are exposed via DAPLink which provides: 296 297- Serial Wire Debug (SWD). 298- USB Mass Storage Device (USBMSD). 299- UART. 300- Remote reset. 301 302For more details please refer 303to the `DAPLink Website`_. 304 305 306Building a secure only application 307---------------------------------- 308 309 310You can build applications in the usual way. Here is an example for 311the :zephyr:code-sample:`hello_world` application. 312 313.. zephyr-app-commands:: 314 :zephyr-app: samples/hello_world 315 :board: v2m_musca_b1 316 :goals: build 317 318Open a serial terminal (minicom, putty, etc.) with the following settings: 319 320- Speed: 115200 321- Data: 8 bits 322- Parity: None 323- Stop bits: 1 324 325Reset the board, and you should see the following message on the corresponding 326serial port: 327 328.. code-block:: console 329 330 Hello World! musca_b1 331 332Building a secure/non-secure with Trusted Firmware 333-------------------------------------------------- 334 335The process requires five steps: 336 3371. Build Trusted Firmware (tfm). 3382. Import it as a library to the Zephyr source folder. 3393. Build Zephyr with a non-secure configuration. 3404. Merge the two binaries together and sign them. 3415. Concatenate the bootloader with the signed image blob. 342 343In order to build tfm please refer to `Trusted Firmware M Guide`_. 344Follow the build steps for AN521 target while replacing the platform with 345``-DTARGET_PLATFORM=MUSCA_B1`` and compiler (if required) with ``-DCOMPILER=GNUARM`` 346 347Copy over tfm as a library to the Zephyr project source and create a shortcut 348for the secure veneers and necessary header files. All files are in the install 349folder after TF-M built. 350 351Uploading an application to V2M Musca B1 352---------------------------------------- 353 354Applications must be converted to Intel's hex format before being flashed to a 355V2M Musca B1. An optional bootloader can be prepended to the image. 356The QSPI flash base address alias is 0x0, and the eFlash base address alias is 3570xA000000. 358The image offset is calculated by adding the flash offset to the 359bootloader partition size. 360 361A third-party tool (srecord) is used to generate the Intel formatted hex image. 362For more information refer to the `Srecord Manual`_. 363 364.. code-block:: bash 365 366 srec_cat $BIN_BOOTLOADER -Binary -offset $FLASH_OFFSET $BIN_SNS -Binary -offset $IMAGE_OFFSET -o $HEX_FLASHABLE -Intel 367 368 # For a 128K bootloader IMAGE_OFFSET = $FLASH_OFFSET + 0x20000 369 srec_cat $BIN_BOOTLOADER -Binary -offset 0xA000000 $BIN_SNS -Binary -offset 0xA020000 -o $HEX_FLASHABLE -Intel 370 371Connect the V2M Musca B1 to your host computer using the USB port. You should 372see a USB connection exposing a Mass Storage (MUSCA_B) and a USB Serial Port. 373Copy the generated ``zephyr.hex`` in the MUSCA_B drive. 374 375Reset the board, and you should see the following message on the corresponding 376serial port: 377 378.. code-block:: console 379 380 Hello World! musca_b1 381 382 383.. _V2M Musca B1 Website: 384 https://developer.arm.com/Tools%20and%20Software/Musca-B1%20Test%20Chip%20Board 385 386.. _Musca B1 Technical Reference Manual (TRM): 387 https://developer.arm.com/documentation/101312/latest/ 388 389.. _DAPLink Website: 390 https://github.com/ARMmbed/DAPLink 391 392.. _Cortex M33 Generic User Guide: 393 https://developer.arm.com/documentation/100235/latest/ 394 395.. _Trusted Firmware M Guide: 396 https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html 397 398.. _Corelink SSE-200 Subsystem: 399 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200 400 401.. _Srecord Manual: 402 https://srecord.sourceforge.net/man/man1/srec_cat.1.html 403 404.. _IDAU: 405 https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU- 406 407.. _AMBA®: 408 https://developer.arm.com/products/architecture/system-architectures/amba 409
