1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/clock/nxp_s32k146_clock.h>
8#include <nxp/nxp_s32k1xx.dtsi>
9
10/ {
11	cpus {
12		cpu@0 {
13			compatible = "arm,cortex-m4f";
14		};
15	};
16
17	soc {
18		/*
19		 * SRAM_L and SRAM_U ranges form a contiguous block but misaligned
20		 * and burst accesses cannot occur across the 0x20000000 boundary
21		 * that separates the two SRAM arrays. Hence, treat the two arrays
22		 * as separate memory ranges.
23		 */
24		sram_l: sram@1fff0000 {
25			compatible = "mmio-sram";
26			reg = <0x1fff0000 DT_SIZE_K(64)>;
27		};
28
29		sram_u: sram@20000000 {
30			compatible = "mmio-sram";
31			reg = <0x20000000 DT_SIZE_K(60)>;
32		};
33	};
34};
35
36/delete-node/ &lpi2c1;
37/delete-node/ &ftm6;
38/delete-node/ &ftm7;
39
40&nvic {
41	arm,num-irq-priority-bits = <4>;
42};
43
44&ftfc {
45	flash0: flash@0 {
46		compatible = "soc-nv-flash";
47		reg = <0 DT_SIZE_M(1)>;
48		erase-block-size = <DT_SIZE_K(4)>;
49		write-block-size = <8>;
50	};
51};
52
53&lpuart2 {
54	clocks = <&clock NXP_S32_LPUART2_CLK>;
55};
56
57&lpspi1 {
58	clocks = <&clock NXP_S32_LPSPI1_CLK>;
59};
60
61&lpspi2 {
62	clocks = <&clock NXP_S32_LPSPI2_CLK>;
63};
64
65&flexcan0 {
66	interrupts = <78 0>, <79 0>, <80 0>, <81 0>, <82 0>;
67	interrupt-names = "warning", "error", "wake-up", "mb-0-15", "mb-16-31";
68};
69
70&flexcan1 {
71	interrupts = <85 0>, <86 0>, <88 0>, <89 0>;
72	interrupt-names = "warning", "error", "mb-0-15", "mb-16-31";
73	clocks = <&clock NXP_S32_FLEXCAN1_CLK>;
74};
75
76&flexcan2 {
77	interrupts = <92 0>, <93 0>, <95 0>;
78	interrupt-names = "warning", "error", "mb-0-15";
79	clocks = <&clock NXP_S32_FLEXCAN2_CLK>;
80};
81