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/Zephyr-latest/drivers/gpio/
Dgpio_lpc11u6x.c5 * SPDX-License-Identifier: Apache-2.0
21 #include <zephyr/irq.h>
27 /* Offset from syscon base address. */
38 * not used by this driver. A 0x2000 offset is applied to skip them.
76 * @brief Structure for resources and information shared between GPIO ports.
78 * This structure is included by all the per-port private configuration.
79 * It gathers all the resources and information shared between all the GPIO
93 const struct gpio_lpc11u6x_shared *shared; member
108 const struct gpio_lpc11u6x_config *config = port->config; in gpio_lpc11u6x_pin_configure()
110 (config->shared->gpio_base + LPC11U6X_GPIO_REGS); in gpio_lpc11u6x_pin_configure()
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Dgpio_ambiq.c5 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/irq.h>
24 uint32_t offset; member
38 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_pin_configure()
42 pin += dev_cfg->offset; in ambiq_gpio_pin_configure()
81 pin += (dev_cfg->offset >> 2); in ambiq_gpio_pin_configure()
122 ret = -ENOTSUP; in ambiq_gpio_pin_configure()
131 const struct ambiq_gpio_config *const dev_cfg = dev->config; in ambiq_gpio_get_config()
135 pin += dev_cfg->offset; in ambiq_gpio_get_config()
168 pin += (dev_cfg->offset >> 2); in ambiq_gpio_get_config()
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/Zephyr-latest/scripts/build/
Dgen_isr_tables_parser_local.py7 # SPDX-License-Identifier: Apache-2.0
14 /* AUTO-GENERATED by gen_isr_tables.py, do not edit! */
25 /* For this parser to work, we have to be sure that shared interrupts table entry
31 "Shared ISR and ISR table entries layout do not match");
35 "Shared ISR and ISR table entries layout do not match");
39 "Shared ISR and ISR table entries layout do not match");
48 - intlist_data: The binnary data from intlist section
49 - config: The configuration object
50 - log: The logging object, has to have error and debug methods
65 uint32_t num_vectors; <- typically CONFIG_NUM_IRQS
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Dgen_isr_tables_parser_carrays.py7 # SPDX-License-Identifier: Apache-2.0
14 /* AUTO-GENERATED by gen_isr_tables.py, do not edit! */
35 - intlist_data: The binnary data from intlist section
36 - config: The configuration object
37 - log: The logging object, has to have error and debug methods
50 uint32_t num_vectors; <- typically CONFIG_NUM_IRQS
51 struct _isr_list isrs[]; <- Usually of smaller size than num_vectors
58 /** IRQ line number */
59 int32_t irq;
60 /** Flags for this IRQ, see ISR_FLAG_* definitions */
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/Zephyr-latest/dts/bindings/dma/
Dnxp,mcux-edma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
30 The offset value for obtaining DMAMUX register index from DMAMUX channel.
33 channel-gap:
47 irq-shared-offset:
51 Describes an offset between two channels share the same interrupt entry.
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/Zephyr-latest/include/zephyr/drivers/pcie/
Dmsi.h4 * SPDX-License-Identifier: Apache-2.0
29 unsigned int irq; member
86 * @param flags Arch-specific IRQ configuration flag
103 * @param irq The IRQ we wish to trigger via MSI.
106 * @return A (32-bit) value for the MSI MAP register.
108 extern uint32_t pcie_msi_map(unsigned int irq,
117 * @param irq The IRQ we wish to trigger via MSI.
119 * @return A (16-bit) value for MSI MDR register.
121 extern uint16_t pcie_msi_mdr(unsigned int irq,
130 * @param irq The IRQ we wish to trigger via MSI.
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_dw_ace.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/arch/xtensa/irq.h>
18 #include <zephyr/irq.h>
22 * architectural IRQ 4 (see below), run by a Designware interrupt
25 * (i.e. interrupts 0-31 are Xtensa IRQs, 32 represents DW input 0,
28 * That IRQ 4 indeed has an interrupt type of "EXTERN_LEVEL" and an
30 * IRQ 1 and a level 3 on IRQ 6, but nothing seems wired there. Note
31 * that this level 2 ISR is also shared with the CCOUNT timer on IRQ3.
49 * + Drivers manage ACE_DINT themselves, as there are device-specific
51 * core-asymmetric interrupt routing needs to happen, it happens
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/Zephyr-latest/dts/bindings/serial/
Dinfineon,xmc4xxx-uart.yaml3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 input-src:
20 - "DX0A"
21 - "DX0B"
22 - "DX0C"
23 - "DX0D"
24 - "DX0E"
25 - "DX0F"
26 - "DX0G"
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/Zephyr-latest/drivers/dma/
Ddma_stm32.c5 * SPDX-License-Identifier: Apache-2.0
21 #include <zephyr/irq.h>
72 const struct dma_stm32_config *config = dev->config; in dma_stm32_dump_stream_irq()
73 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_dump_stream_irq()
80 const struct dma_stm32_config *config = dev->config; in dma_stm32_clear_stream_irq()
81 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_clear_stream_irq()
90 const struct dma_stm32_config *config = dev->config; in dma_stm32_irq_handler()
91 DMA_TypeDef *dma = (DMA_TypeDef *)(config->base); in dma_stm32_irq_handler()
95 __ASSERT_NO_MSG(id < config->max_streams); in dma_stm32_irq_handler()
97 stream = &config->streams[id]; in dma_stm32_irq_handler()
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/Zephyr-latest/doc/kernel/services/
Dinterrupts.rst24 * An **interrupt request (IRQ) signal** that triggers the ISR.
25 * A **priority level** associated with the IRQ.
31 Only a single ISR can be associated with a specific IRQ at any given time.
43 in mid-execution if a higher priority interrupt is signaled. The lower
62 Multi-level Interrupt Handling
65 A hardware platform can support more interrupt lines than natively-provided
75 A unique 32-bit interrupt number is assigned with information
77 Service Routine (ISR). Each interrupt level is given a byte within this 32-bit
81 .. code-block:: none
93 * '-' means interrupt line and is numbered from 0 (right most).
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/Zephyr-latest/drivers/dai/intel/ssp/
Dssp.h4 * SPDX-License-Identifier: Apache-2.0
30 #include "dai-params-intel-ipc3.h"
31 #include "dai-params-intel-ipc4.h"
34 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
37 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
46 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1)
80 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly.
85 * Input for source is shared by all outputs coming from that source
89 * to change shared input clock.
101 * change shared clock
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/Zephyr-latest/drivers/espi/
Dhost_subs_npcx.c4 * SPDX-License-Identifier: Apache-2.0
13 * This file contains the drivers of NPCX Host Sub-Modules that serve as an
16 * +------------+
17 * | Serial |---> TXD
18 * +<--->| Port |<--- RXD
19 * | | |<--> ...
20 * | +------------+
21 * | +------------+ |
22 * +------------+ |<--->| KBC & PM |<--->|
23 * eSPI_CLK --->| eSPI Bus | | | Channels | |
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/Zephyr-latest/drivers/adc/
Dadc_gd32.c4 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/irq.h>
29 * @brief gd32 adc irq have some special cases as below:
31 * 2. adc0 and adc1 share the same irq number.
32 * 3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
34 * To cover this cases, gd32_adc driver use node-label 'adc0', 'adc1' and
35 * 'adc2' to handle gd32 adc irq config directly.'
37 * @note Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
153 struct adc_gd32_data *data = dev->data; in adc_gd32_isr()
154 const struct adc_gd32_config *cfg = dev->config; in adc_gd32_isr()
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/Zephyr-latest/subsys/bluetooth/controller/
DKconfig.ll_sw_split3 # Copyright (c) 2016-2017 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
120 # Hidden, Controller's Co-Operative high priority Rx thread stack size.
125 # Hidden, Controller's Co-Operative Rx thread stack size.
152 https://www.bluetooth.com/specifications/assigned-numbers/company-identifiers
168 Legacy Non-Directed Advertising mode.
180 zero-based numbering. When using with Zephyr host this option can be
233 module-str = "Bluetooth Controller ISO-AL"
237 bool "ISO-AL verbose debug logging"
241 Use this option to enable ISO-AL verbose debug logging.
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/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2015-2021, Linaro Limited
11 * This file is exported by OP-TEE and is in kept in sync between secure
70 * Normal cached memory (write-back), shareable for SMP systems and not
78 * 32-bit registers.
86 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
110 * Used by non-secure world to figure out which Trusted OS is installed.
113 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
123 * Used by non-secure world to figure out which version of the Trusted OS
127 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
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/Zephyr-latest/arch/x86/core/intel64/
Dlocore.S3 * SPDX-License-Identifier: Apache-2.0
22 /* Long mode, no-execute, syscall */
25 /* Paging, write-protect */
75 /* Use 32-bit instructions due to assembler fussiness with large
85 .word __X86_TSS64_SIZEOF-1
92 /* The .locore section begins the page-aligned initialization region
96 * ACRN...) who hard-coded the address by inspecting _start on a
97 * non-SMP build.
108 * scribble over it with 8 0x90 bytes (which is the 1-byte NOP) and be
129 * First, we move to 32-bit protected mode, and set up the
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/Zephyr-latest/include/zephyr/drivers/can/
Dcan_mcan.h5 * SPDX-License-Identifier: Apache-2.0
399 * @name Indexes for the cells in the devicetree bosch,mram-cfg property
402 * These match the description of the cells in the bosch,m_can-base devicetree binding.
406 /** offset cell index */
408 /** std-filter-elements cell index */
410 /** ext-filter-elements cell index */
412 /** rx-fifo0-elements cell index */
414 /** rx-fifo1-elements cell index */
416 /** rx-buffer-elements cell index */
418 /** tx-event-fifo-elements cell index */
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/Zephyr-latest/dts/arm/nxp/
Dnxp_ke1xz.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "armv6-m.dtsi"
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
11 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
17 zephyr,flash-controller = &ftfe;
21 #address-cells = <1>;
22 #size-cells = <0>;
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Dnxp_rt11xx.dtsi2 * Copyright 2021,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/power/imx_spc.h>
15 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
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Dnxp_rt6xx_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
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/Zephyr-latest/drivers/ethernet/
Deth_esp32.c4 * SPDX-License-Identifier: Apache-2.0
66 struct eth_esp32_dev_data *const dev_data = dev->data; in eth_esp32_set_config()
67 int ret = -ENOTSUP; in eth_esp32_set_config()
71 memcpy(dev_data->mac_addr, config->mac_address.addr, 6); in eth_esp32_set_config()
72 emac_hal_set_address(&dev_data->hal, dev_data->mac_addr); in eth_esp32_set_config()
73 net_if_set_link_addr(dev_data->iface, dev_data->mac_addr, in eth_esp32_set_config()
74 sizeof(dev_data->mac_addr), in eth_esp32_set_config()
87 struct eth_esp32_dev_data *dev_data = dev->data; in eth_esp32_send()
90 if (net_pkt_read(pkt, dev_data->txb, len)) { in eth_esp32_send()
91 return -EIO; in eth_esp32_send()
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/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h4 * SPDX-License-Identifier: Apache-2.0
18 * NPCX register structure size/offset checking macro function to mitigate
20 * must meet the alignment requirement of cortex-m4.
27 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \ argument
28 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
29 "Failed in offset check of register structure member!")
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
90 /* 0x102: High-Frequency Reference Divisor I */
92 /* 0x104: High-Frequency Reference Divisor F */
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/Zephyr-latest/drivers/dai/intel/dmic/
Ddmic.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/irq.h>
30 /* global data shared between all dmic instances */
33 /* Helper macro to read 64-bit data using two 32-bit data read */
40 * fairly accurately exponent for x in range -2.0 .. +2.0. The iteration
61 p = num * x; /* Q9.23 x Q3.29 -> Q12.52 */ in exp_small_fixed()
79 if (x < Q_CONVERT_FLOAT(-11.5, 27)) { in exp_fixed()
110 if (db < Q_CONVERT_FLOAT(-100.0, 24)) { in db2lin_fixed()
122 uint32_t dest = dmic->reg_base + reg; in dai_dmic_update_bits()
130 sys_write32(val, dmic->reg_base + reg); in dai_dmic_write()
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/Zephyr-latest/drivers/can/
Dcan_stm32_bxcan.c5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/irq.h>
67 CAN_TypeDef *master_can; /*!< CAN Registers for shared filter */
74 * Mutex to prevent simultaneous access to filter registers shared between CAN1
82 can_tx_callback_t callback = mb->tx_callback; in can_stm32_signal_tx_complete()
85 callback(dev, status, mb->callback_arg); in can_stm32_signal_tx_complete()
86 mb->tx_callback = NULL; in can_stm32_signal_tx_complete()
94 if (mbox->RIR & CAN_RI0R_IDE) { in can_stm32_rx_fifo_pop()
95 frame->id = mbox->RIR >> CAN_RI0R_EXID_Pos; in can_stm32_rx_fifo_pop()
96 frame->flags |= CAN_FRAME_IDE; in can_stm32_rx_fifo_pop()
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/Zephyr-latest/doc/kernel/services/smp/
Dsmp.rst26 non-Zephyr code).
50 also atomically validates that a shared lock variable has been
54 on top of the pre-existing :c:struct:`atomic_` layer (itself usually
58 One important difference between IRQ locks and spinlocks is that the
65 re-acquire it or it will deadlock (it is perfectly legal to nest
71 recursive semantics above, spinlocks in single-CPU contexts produce
72 identical code to legacy IRQ locks. In fact the entirety of the
85 and that it is re-acquired when necessary to restore the lock state
93 IRQ lock is global, means that code expecting to be run in an SMP
109 :c:func:`k_thread_cpu_mask_enable` will re-enable execution. There are also
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