4  * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/irq.h>
29  * @brief gd32 adc irq have some special cases as below:
31  *   2. adc0 and adc1 share the same irq number.
32  *   3. For gd32f4xx, adc2 share the same irq number with adc0 and adc1.
34  * To cover this cases, gd32_adc driver use node-label 'adc0', 'adc1' and
35  * 'adc2' to handle gd32 adc irq config directly.'
37  * @note Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
153 	struct adc_gd32_data *data = dev->data;  in adc_gd32_isr()
154 	const struct adc_gd32_config *cfg = dev->config;  in adc_gd32_isr()
156 	if (ADC_STAT(cfg->reg) & ADC_STAT_EOC) {  in adc_gd32_isr()
157 		*data->buffer++ = ADC_RDATA(cfg->reg);  in adc_gd32_isr()
160 		ADC_CTL0(cfg->reg) &= ~ADC_CTL0_EOCIE;  in adc_gd32_isr()
162 		ADC_STAT(cfg->reg) &= ~ADC_STAT_EOC;  in adc_gd32_isr()
164 		adc_context_on_sampling_done(&data->ctx, dev);  in adc_gd32_isr()
171 	const struct device *dev = data->dev;  in adc_context_start_sampling()
172 	const struct adc_gd32_config *cfg = dev->config;  in adc_context_start_sampling()
174 	data->repeat_buffer = data->buffer;  in adc_context_start_sampling()
177 	ADC_CTL0(cfg->reg) |= ADC_CTL0_EOCIE;  in adc_context_start_sampling()
180 	ADC_CTL1(cfg->reg) |= ADC_CTL1_SWRCST;  in adc_context_start_sampling()
189 		data->buffer = data->repeat_buffer;  in adc_context_update_buffer_pointer()
195 	ADC_CTL1(cfg->reg) |= ADC_CTL1_RSTCLB;  in adc_gd32_calibration()
197 	while (ADC_CTL1(cfg->reg) & ADC_CTL1_RSTCLB) {  in adc_gd32_calibration()
200 	ADC_CTL1(cfg->reg) |= ADC_CTL1_CLB;  in adc_gd32_calibration()
202 	while (ADC_CTL1(cfg->reg) & ADC_CTL1_CLB) {  in adc_gd32_calibration()
209 	uint8_t index = 0, offset;  in adc_gd32_configure_sampt()  local
214 			return -EINVAL;  in adc_gd32_configure_sampt()
224 			return -ENOTSUP;  in adc_gd32_configure_sampt()
229 		offset = SPT_WIDTH * channel;  in adc_gd32_configure_sampt()
230 		ADC_SAMPT1(cfg->reg) &= ~(ADC_SAMPTX_SPTN << offset);  in adc_gd32_configure_sampt()
231 		ADC_SAMPT1(cfg->reg) |= table_samp_time[index] << offset;  in adc_gd32_configure_sampt()
233 		offset = SPT_WIDTH * (channel - SAMPT1_SIZE);  in adc_gd32_configure_sampt()
234 		ADC_SAMPT0(cfg->reg) &= ~(ADC_SAMPTX_SPTN << offset);  in adc_gd32_configure_sampt()
235 		ADC_SAMPT0(cfg->reg) |= table_samp_time[index] << offset;  in adc_gd32_configure_sampt()
244 	const struct adc_gd32_config *cfg = dev->config;  in adc_gd32_channel_setup()
246 	if (chan_cfg->gain != ADC_GAIN_1) {  in adc_gd32_channel_setup()
248 		return -ENOTSUP;  in adc_gd32_channel_setup()
251 	if (chan_cfg->reference != ADC_REF_INTERNAL) {  in adc_gd32_channel_setup()
253 		return -ENOTSUP;  in adc_gd32_channel_setup()
256 	if (chan_cfg->differential) {  in adc_gd32_channel_setup()
258 		return -ENOTSUP;  in adc_gd32_channel_setup()
261 	if (chan_cfg->channel_id >= cfg->channels) {  in adc_gd32_channel_setup()
262 		LOG_ERR("Invalid channel (%u)", chan_cfg->channel_id);  in adc_gd32_channel_setup()
263 		return -EINVAL;  in adc_gd32_channel_setup()
266 	return adc_gd32_configure_sampt(cfg, chan_cfg->channel_id,  in adc_gd32_channel_setup()
267 					chan_cfg->acquisition_time);  in adc_gd32_channel_setup()
273 	struct adc_gd32_data *data = dev->data;  in adc_gd32_start_read()
274 	const struct adc_gd32_config *cfg = dev->config;  in adc_gd32_start_read()
278 	index = find_lsb_set(sequence->channels) - 1;  in adc_gd32_start_read()
279 	if (sequence->channels > BIT(index)) {  in adc_gd32_start_read()
281 		return -ENOTSUP;  in adc_gd32_start_read()
284 	switch (sequence->resolution) {  in adc_gd32_start_read()
298 		return -EINVAL;  in adc_gd32_start_read()
304 	ADC_CTL0(cfg->reg) &= ~ADC_CTL0_DRES;  in adc_gd32_start_read()
305 	ADC_CTL0(cfg->reg) |= CTL0_DRES(resolution_id);  in adc_gd32_start_read()
308 	ADC_OVSAMPCTL(cfg->reg) &= ~ADC_OVSAMPCTL_DRES;  in adc_gd32_start_read()
309 	ADC_OVSAMPCTL(cfg->reg) |= OVSAMPCTL_DRES(resolution_id);  in adc_gd32_start_read()
311 	ADC_OVSCR(cfg->reg) &= ~ADC_OVSCR_DRES;  in adc_gd32_start_read()
312 	ADC_OVSCR(cfg->reg) |= OVSCR_DRES(resolution_id);  in adc_gd32_start_read()
315 	if (sequence->calibrate) {  in adc_gd32_start_read()
320 	ADC_RSQ2(cfg->reg) &= ~ADC_RSQX_RSQN;  in adc_gd32_start_read()
321 	ADC_RSQ2(cfg->reg) = index;  in adc_gd32_start_read()
323 	data->buffer = sequence->buffer;  in adc_gd32_start_read()
325 	adc_context_start_read(&data->ctx, sequence);  in adc_gd32_start_read()
327 	return adc_context_wait_for_completion(&data->ctx);  in adc_gd32_start_read()
333 	struct adc_gd32_data *data = dev->data;  in adc_gd32_read()
336 	adc_context_lock(&data->ctx, false, NULL);  in adc_gd32_read()
338 	adc_context_release(&data->ctx, error);  in adc_gd32_read()
348 	struct adc_gd32_data *data = dev->data;  in adc_gd32_read_async()
351 	adc_context_lock(&data->ctx, true, async);  in adc_gd32_read_async()
353 	adc_context_release(&data->ctx, error);  in adc_gd32_read_async()
369 	struct adc_gd32_data *data = dev->data;  in adc_gd32_init()
370 	const struct adc_gd32_config *cfg = dev->config;  in adc_gd32_init()
373 	data->dev = dev;  in adc_gd32_init()
375 	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);  in adc_gd32_init()
382 	rcu_adc_clock_config(cfg->rcu_clock_source);  in adc_gd32_init()
386 			       (clock_control_subsys_t)&cfg->clkid);  in adc_gd32_init()
388 	(void)reset_line_toggle_dt(&cfg->reset);  in adc_gd32_init()
395 	ADC_CTL1(cfg->reg) &= ~ADC_CTL1_ETSRC;  in adc_gd32_init()
396 	ADC_CTL1(cfg->reg) |= CTL1_ETSRC(7);  in adc_gd32_init()
399 	ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;  in adc_gd32_init()
403 	ADC_CTL1(cfg->reg) |= ADC_CTL1_ETSRC;  in adc_gd32_init()
404 	ADC_CTL1(cfg->reg) |= ADC_CTL1_ETERC;  in adc_gd32_init()
408 	ADC_CTL1(cfg->reg) |= ADC_CTL1_ADCON;  in adc_gd32_init()
412 	cfg->irq_config_func();  in adc_gd32_init()
414 	adc_context_unlock_unconditionally(&data->ctx);  in adc_gd32_init()
421 	const struct adc_gd32_config *cfg_##n = dev_##n->config;				\
423 	if ((cfg_##n->irq_num == active_irq) &&							\
424 		(ADC_CTL0(cfg_##n->reg) & ADC_CTL0_EOCIE)) {					\
430 	const struct adc_gd32_config *cfg = dev->config;  in adc_gd32_global_irq_handler()
432 	LOG_DBG("global irq handler: %u", cfg->irq_num);  in adc_gd32_global_irq_handler()
434 	DT_INST_FOREACH_STATUS_OKAY_VARGS(HANDLE_SHARED_IRQ, (cfg->irq_num));  in adc_gd32_global_irq_handler()
448 	/* Shared irq config default to adc0. */  in adc_gd32_global_irq_cfg()
466 	/* gd32f4xx adc2 share the same irq number with adc0 and adc1. */  in adc_gd32_global_irq_cfg()