1 /*
2 * Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT espressif_esp32_eth
8
9 #include <ethernet/eth_stats.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/net/ethernet.h>
14 #include <zephyr/net/phy.h>
15
16 #include <esp_attr.h>
17 #include <esp_mac.h>
18 #include <hal/emac_hal.h>
19 #include <hal/emac_ll.h>
20 #include <soc/rtc.h>
21 #include <soc/io_mux_reg.h>
22 #include <clk_ctrl_os.h>
23
24 #include "eth.h"
25
26 LOG_MODULE_REGISTER(eth_esp32, CONFIG_ETHERNET_LOG_LEVEL);
27
28 #define MAC_RESET_TIMEOUT_MS 100
29
30 struct eth_esp32_dma_data {
31 uint8_t descriptors[
32 CONFIG_ETH_DMA_RX_BUFFER_NUM * sizeof(eth_dma_rx_descriptor_t) +
33 CONFIG_ETH_DMA_TX_BUFFER_NUM * sizeof(eth_dma_tx_descriptor_t)];
34 uint8_t rx_buf[CONFIG_ETH_DMA_RX_BUFFER_NUM][CONFIG_ETH_DMA_BUFFER_SIZE];
35 uint8_t tx_buf[CONFIG_ETH_DMA_TX_BUFFER_NUM][CONFIG_ETH_DMA_BUFFER_SIZE];
36 };
37
38 struct eth_esp32_dev_data {
39 struct net_if *iface;
40 uint8_t mac_addr[6];
41 emac_hal_context_t hal;
42 struct eth_esp32_dma_data *dma;
43 uint8_t txb[NET_ETH_MAX_FRAME_SIZE];
44 uint8_t rxb[NET_ETH_MAX_FRAME_SIZE];
45 uint8_t *dma_rx_buf[CONFIG_ETH_DMA_RX_BUFFER_NUM];
46 uint8_t *dma_tx_buf[CONFIG_ETH_DMA_TX_BUFFER_NUM];
47 struct k_sem int_sem;
48
49 K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_ESP32_RX_THREAD_STACK_SIZE);
50 struct k_thread rx_thread;
51 };
52
53 static const struct device *eth_esp32_phy_dev = DEVICE_DT_GET(
54 DT_INST_PHANDLE(0, phy_handle));
55
eth_esp32_caps(const struct device * dev)56 static enum ethernet_hw_caps eth_esp32_caps(const struct device *dev)
57 {
58 ARG_UNUSED(dev);
59 return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T;
60 }
61
eth_esp32_set_config(const struct device * dev,enum ethernet_config_type type,const struct ethernet_config * config)62 static int eth_esp32_set_config(const struct device *dev,
63 enum ethernet_config_type type,
64 const struct ethernet_config *config)
65 {
66 struct eth_esp32_dev_data *const dev_data = dev->data;
67 int ret = -ENOTSUP;
68
69 switch (type) {
70 case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
71 memcpy(dev_data->mac_addr, config->mac_address.addr, 6);
72 emac_hal_set_address(&dev_data->hal, dev_data->mac_addr);
73 net_if_set_link_addr(dev_data->iface, dev_data->mac_addr,
74 sizeof(dev_data->mac_addr),
75 NET_LINK_ETHERNET);
76 ret = 0;
77 break;
78 default:
79 break;
80 }
81
82 return ret;
83 }
84
eth_esp32_send(const struct device * dev,struct net_pkt * pkt)85 static int eth_esp32_send(const struct device *dev, struct net_pkt *pkt)
86 {
87 struct eth_esp32_dev_data *dev_data = dev->data;
88 size_t len = net_pkt_get_len(pkt);
89
90 if (net_pkt_read(pkt, dev_data->txb, len)) {
91 return -EIO;
92 }
93
94 uint32_t sent_len = emac_hal_transmit_frame(&dev_data->hal, dev_data->txb, len);
95
96 int res = len == sent_len ? 0 : -EIO;
97
98 return res;
99 }
100
eth_esp32_rx(struct eth_esp32_dev_data * const dev_data,uint32_t * frames_remaining)101 static struct net_pkt *eth_esp32_rx(
102 struct eth_esp32_dev_data *const dev_data, uint32_t *frames_remaining)
103 {
104 uint32_t free_rx_descriptor;
105 uint32_t receive_len = emac_hal_receive_frame(
106 &dev_data->hal, dev_data->rxb, sizeof(dev_data->rxb),
107 frames_remaining, &free_rx_descriptor);
108 if (receive_len == 0) {
109 /* Nothing to receive */
110 return NULL;
111 }
112
113 struct net_pkt *pkt = net_pkt_rx_alloc_with_buffer(
114 dev_data->iface, receive_len, AF_UNSPEC, 0, K_MSEC(100));
115 if (pkt == NULL) {
116 eth_stats_update_errors_rx(dev_data->iface);
117 LOG_ERR("Could not allocate rx buffer");
118 return NULL;
119 }
120
121 if (net_pkt_write(pkt, dev_data->rxb, receive_len) != 0) {
122 LOG_ERR("Unable to write frame into the pkt");
123 eth_stats_update_errors_rx(dev_data->iface);
124 net_pkt_unref(pkt);
125 return NULL;
126 }
127
128 return pkt;
129 }
130
eth_esp32_rx_thread(void * arg1,void * arg2,void * arg3)131 FUNC_NORETURN static void eth_esp32_rx_thread(void *arg1, void *arg2, void *arg3)
132 {
133 const struct device *dev = arg1;
134 struct eth_esp32_dev_data *const dev_data = dev->data;
135
136 ARG_UNUSED(arg2);
137 ARG_UNUSED(arg3);
138
139 while (true) {
140 k_sem_take(&dev_data->int_sem, K_FOREVER);
141
142 uint32_t frames_remaining;
143
144 do {
145 struct net_pkt *pkt = eth_esp32_rx(
146 dev_data, &frames_remaining);
147 if (pkt == NULL) {
148 break;
149 }
150
151 if (net_recv_data(dev_data->iface, pkt) < 0) {
152 /* Upper layers are not ready to receive packets */
153 net_pkt_unref(pkt);
154 }
155 } while (frames_remaining > 0);
156 }
157 }
158
eth_esp32_isr(void * arg)159 IRAM_ATTR static void eth_esp32_isr(void *arg)
160 {
161 const struct device *dev = arg;
162 struct eth_esp32_dev_data *const dev_data = dev->data;
163 uint32_t intr_stat = emac_ll_get_intr_status(dev_data->hal.dma_regs);
164
165 emac_ll_clear_corresponding_intr(dev_data->hal.dma_regs, intr_stat);
166
167 if (intr_stat & EMAC_LL_DMA_RECEIVE_FINISH_INTR) {
168 k_sem_give(&dev_data->int_sem);
169 }
170 }
171
generate_mac_addr(uint8_t mac_addr[6])172 static int generate_mac_addr(uint8_t mac_addr[6])
173 {
174 int res = 0;
175 #if DT_INST_PROP(0, zephyr_random_mac_address)
176 gen_random_mac(mac_addr, 0x24, 0xD7, 0xEB);
177 #elif NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))
178 static const uint8_t addr[6] = DT_INST_PROP(0, local_mac_address);
179
180 memcpy(mac_addr, addr, sizeof(addr));
181 #else
182 if (esp_read_mac(mac_addr, ESP_MAC_ETH) != ESP_OK) {
183 res = -EIO;
184 }
185 #endif
186 return res;
187 }
188
phy_link_state_changed(const struct device * phy_dev,struct phy_link_state * state,void * user_data)189 static void phy_link_state_changed(const struct device *phy_dev,
190 struct phy_link_state *state,
191 void *user_data)
192 {
193 const struct device *dev = (const struct device *)user_data;
194 struct eth_esp32_dev_data *const dev_data = dev->data;
195
196 ARG_UNUSED(phy_dev);
197
198 if (state->is_up) {
199 net_eth_carrier_on(dev_data->iface);
200 } else {
201 net_eth_carrier_off(dev_data->iface);
202 }
203 }
204
205 #if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
emac_config_apll_clock(void)206 static int emac_config_apll_clock(void)
207 {
208 uint32_t expt_freq = MHZ(50);
209 uint32_t real_freq = 0;
210 esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
211
212 if (ret == ESP_ERR_INVALID_ARG) {
213 LOG_ERR("Set APLL clock coefficients failed");
214 return -EIO;
215 }
216
217 if (ret == ESP_ERR_INVALID_STATE) {
218 LOG_INF("APLL is occupied already, it is working at %d Hz", real_freq);
219 }
220
221 /* If the difference of real APLL frequency
222 * is not within 50 ppm, i.e. 2500 Hz,
223 * the APLL is unavailable
224 */
225 if (abs((int)real_freq - (int)expt_freq) > 2500) {
226 LOG_ERR("The APLL is working at an unusable frequency");
227 return -EIO;
228 }
229
230 return 0;
231 }
232 #endif /* DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios) */
233
eth_esp32_initialize(const struct device * dev)234 int eth_esp32_initialize(const struct device *dev)
235 {
236 struct eth_esp32_dev_data *const dev_data = dev->data;
237 int res;
238
239 k_sem_init(&dev_data->int_sem, 0, 1);
240
241 const struct device *clock_dev =
242 DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(eth)));
243 clock_control_subsys_t clock_subsys =
244 (clock_control_subsys_t)DT_CLOCKS_CELL(DT_NODELABEL(eth), offset);
245
246 /* clock is shared, so do not bail out if already enabled */
247 res = clock_control_on(clock_dev, clock_subsys);
248 if (res < 0 && res != -EALREADY) {
249 goto err;
250 }
251
252 /* Convert 2D array DMA buffers to arrays of pointers */
253 for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) {
254 dev_data->dma_rx_buf[i] = dev_data->dma->rx_buf[i];
255 }
256 for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) {
257 dev_data->dma_tx_buf[i] = dev_data->dma->tx_buf[i];
258 }
259
260 emac_hal_init(&dev_data->hal, dev_data->dma->descriptors,
261 dev_data->dma_rx_buf, dev_data->dma_tx_buf);
262
263 /* Configure ISR */
264 res = esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(eth), 0, irq),
265 ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(eth), 0, priority)) |
266 ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(eth), 0, flags)) |
267 ESP_INTR_FLAG_IRAM,
268 eth_esp32_isr,
269 (void *)dev,
270 NULL);
271 if (res != 0) {
272 goto err;
273 }
274
275 /* Configure phy for Media-Independent Interface (MII) or
276 * Reduced Media-Independent Interface (RMII) mode
277 */
278 const char *phy_connection_type = DT_INST_PROP_OR(0,
279 phy_connection_type,
280 "rmii");
281
282 if (strcmp(phy_connection_type, "rmii") == 0) {
283 emac_hal_iomux_init_rmii();
284 #if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
285 BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 ||
286 DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17,
287 "Only GPIO16/17 are allowed as a GPIO REF_CLK source!");
288 int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios);
289 emac_hal_iomux_rmii_clk_output(ref_clk_gpio);
290 emac_ll_clock_enable_rmii_output(dev_data->hal.ext_regs);
291 periph_rtc_apll_acquire();
292 res = emac_config_apll_clock();
293 if (res != 0) {
294 goto err;
295 }
296 rtc_clk_apll_enable(true);
297 #else
298 emac_hal_iomux_rmii_clk_input();
299 emac_ll_clock_enable_rmii_input(dev_data->hal.ext_regs);
300 #endif
301 } else if (strcmp(phy_connection_type, "mii") == 0) {
302 emac_hal_iomux_init_mii();
303 emac_ll_clock_enable_mii(dev_data->hal.ext_regs);
304 } else {
305 res = -EINVAL;
306 goto err;
307 }
308
309 /* Reset mac registers and wait until ready */
310 emac_ll_reset(dev_data->hal.dma_regs);
311 bool reset_success = false;
312
313 for (uint32_t t_ms = 0; t_ms < MAC_RESET_TIMEOUT_MS; t_ms += 10) {
314 /* Busy wait rather than sleep in case kernel is not yet initialized */
315 k_busy_wait(10 * 1000);
316 if (emac_ll_is_reset_done(dev_data->hal.dma_regs)) {
317 reset_success = true;
318 break;
319 }
320 }
321 if (!reset_success) {
322 res = -ETIMEDOUT;
323 goto err;
324 }
325
326 /* Set dma_burst_len as ETH_DMA_BURST_LEN_32 by default */
327 emac_hal_dma_config_t dma_config = { .dma_burst_len = 0 };
328
329 emac_hal_reset_desc_chain(&dev_data->hal);
330 emac_hal_init_mac_default(&dev_data->hal);
331 emac_hal_init_dma_default(&dev_data->hal, &dma_config);
332
333 res = generate_mac_addr(dev_data->mac_addr);
334 if (res != 0) {
335 goto err;
336 }
337 emac_hal_set_address(&dev_data->hal, dev_data->mac_addr);
338
339 k_tid_t tid = k_thread_create(
340 &dev_data->rx_thread, dev_data->rx_thread_stack,
341 K_KERNEL_STACK_SIZEOF(dev_data->rx_thread_stack),
342 eth_esp32_rx_thread,
343 (void *)dev, NULL, NULL,
344 CONFIG_ETH_ESP32_RX_THREAD_PRIORITY,
345 K_ESSENTIAL, K_NO_WAIT);
346 if (IS_ENABLED(CONFIG_THREAD_NAME)) {
347 k_thread_name_set(tid, "esp32_eth");
348 }
349
350 emac_hal_start(&dev_data->hal);
351
352 return 0;
353
354 err:
355 return res;
356 }
357
eth_esp32_phy_get(const struct device * dev)358 static const struct device *eth_esp32_phy_get(const struct device *dev)
359 {
360 ARG_UNUSED(dev);
361 return eth_esp32_phy_dev;
362 }
363
eth_esp32_iface_init(struct net_if * iface)364 static void eth_esp32_iface_init(struct net_if *iface)
365 {
366 const struct device *dev = net_if_get_device(iface);
367 struct eth_esp32_dev_data *dev_data = dev->data;
368
369 dev_data->iface = iface;
370
371 net_if_set_link_addr(iface, dev_data->mac_addr,
372 sizeof(dev_data->mac_addr),
373 NET_LINK_ETHERNET);
374
375 ethernet_init(iface);
376
377 if (device_is_ready(eth_esp32_phy_dev)) {
378 phy_link_callback_set(eth_esp32_phy_dev, phy_link_state_changed,
379 (void *)dev);
380 } else {
381 LOG_ERR("PHY device not ready");
382 }
383
384 /* Do not start the interface until PHY link is up */
385 net_if_carrier_off(iface);
386 }
387
388 static const struct ethernet_api eth_esp32_api = {
389 .iface_api.init = eth_esp32_iface_init,
390 .get_capabilities = eth_esp32_caps,
391 .set_config = eth_esp32_set_config,
392 .get_phy = eth_esp32_phy_get,
393 .send = eth_esp32_send,
394 };
395
396 /* DMA data must be in DRAM */
397 static struct eth_esp32_dma_data eth_esp32_dma_data WORD_ALIGNED_ATTR DRAM_ATTR;
398
399 static struct eth_esp32_dev_data eth_esp32_dev = {
400 .dma = ð_esp32_dma_data,
401 };
402
403 ETH_NET_DEVICE_DT_INST_DEFINE(0,
404 eth_esp32_initialize,
405 NULL,
406 ð_esp32_dev,
407 NULL,
408 CONFIG_ETH_INIT_PRIORITY,
409 ð_esp32_api,
410 NET_ETH_MTU);
411
