1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include "armv6-m.dtsi"
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/kinetis_pcc.h>
11#include <zephyr/dt-bindings/clock/kinetis_scg.h>
12#include <zephyr/dt-bindings/gpio/gpio.h>
13#include <zephyr/dt-bindings/i2c/i2c.h>
14
15/ {
16	chosen {
17		zephyr,flash-controller = &ftfe;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			compatible = "arm,cortex-m0+";
26			clock-frequency = <48000000>;
27			reg = <0>;
28			cpu-power-states = <&idle &stop &pstop1 &pstop2>;
29		};
30
31		power-states {
32			idle: idle {
33				compatible = "zephyr,power-state";
34				power-state-name = "runtime-idle";
35			};
36
37			stop: stop {
38				compatible = "zephyr,power-state";
39				power-state-name = "suspend-to-idle";
40				substate-id = <0>;
41			};
42
43			pstop1: pstop1 {
44				compatible = "zephyr,power-state";
45				power-state-name = "suspend-to-idle";
46				substate-id = <1>;
47			};
48
49			pstop2: pstop2 {
50				compatible = "zephyr,power-state";
51				power-state-name = "suspend-to-idle";
52				substate-id = <2>;
53			};
54		};
55	};
56
57	sram_l: memory@1fffe000 {
58		compatible = "zephyr,memory-region", "mmio-sram";
59		reg = <0x1FFFE000 DT_SIZE_K(8)>;
60		zephyr,memory-region = "SRAML";
61	};
62
63	sram_u: memory@20000000 {
64		compatible = "zephyr,memory-region", "mmio-sram";
65		reg = <0x20000000 DT_SIZE_K(24)>;
66		zephyr,memory-region = "SRAMU";
67	};
68
69	pinctrl: pinctrl {
70		compatible = "nxp,port-pinctrl";
71	};
72
73	soc {
74		scg: scg@40064000 {
75			sosc-mode = <KINETIS_SCG_SOSC_MODE_LOW_POWER>;
76			compatible = "nxp,kinetis-scg";
77			reg = <0x40064000 0x1000>;
78			#clock-cells = <1>;
79
80			sirc_clk: sirc_clk {
81				compatible = "fixed-clock";
82				clock-frequency = <8000000>;
83				#clock-cells = <0>;
84			};
85
86			firc_clk: firc_clk {
87				compatible = "fixed-clock";
88				clock-frequency = <48000000>;
89				#clock-cells = <0>;
90			};
91
92			core_clk: core_clk {
93				compatible = "fixed-factor-clock";
94				clocks = <&firc_clk>;
95				clock-div = <1>;
96				#clock-cells = <0>;
97			};
98
99			bus_clk: bus_clk {
100				compatible = "fixed-factor-clock";
101				clocks = <&core_clk>;
102				clock-div = <4>;
103				#clock-cells = <0>;
104			};
105
106			sircdiv2_clk: sircdiv2_clk {
107				compatible = "fixed-factor-clock";
108				clocks = <&sirc_clk>;
109				clock-div = <2>;
110				#clock-cells = <0>;
111			};
112
113			fircdiv2_clk: fircdiv2_clk {
114				compatible = "fixed-factor-clock";
115				clocks = <&firc_clk>;
116				clock-div = <1>;
117				#clock-cells = <0>;
118			};
119		};
120
121		pcc: pcc@40065000 {
122			compatible = "nxp,kinetis-pcc";
123			reg = <0x40065000 0x1000>;
124			#clock-cells = <2>;
125		};
126
127		ftfe: flash-controller@40020000 {
128			compatible = "nxp,kinetis-ftfe";
129			reg = <0x40020000 0x1000>;
130			interrupts = <5 0>;
131			interrupt-names = "command-complete";
132
133			#address-cells = <1>;
134			#size-cells = <1>;
135
136			flash0: flash@0 {
137				compatible = "soc-nv-flash";
138				reg = <0 DT_SIZE_K(256)>;
139				erase-block-size = <DT_SIZE_K(2)>;
140				write-block-size = <8>;
141			};
142		};
143
144		adc0: adc@4003b000 {
145			compatible = "nxp,adc12";
146			reg = <0x4003b000 0x1000>;
147			interrupts = <15 0>;
148			clocks = <&pcc 0xec KINETIS_PCC_SRC_SIRC_ASYNC>;
149			clk-source = <0>;
150			clk-divider = <1>;
151			status = "disabled";
152			#io-channel-cells = <1>;
153		};
154
155		lpuart0: uart@4006a000 {
156			compatible = "nxp,lpuart";
157			reg = <0x4006a000 0x1000>;
158			interrupts = <12 0>;
159			clocks = <&pcc 0x1a8 KINETIS_PCC_SRC_FIRC_ASYNC>;
160			status = "disabled";
161		};
162
163		lpuart1: uart@4006b000 {
164			compatible = "nxp,lpuart";
165			reg = <0x4006b000 0x1000>;
166			interrupts = <13 0>;
167			clocks = <&pcc 0x1ac KINETIS_PCC_SRC_FIRC_ASYNC>;
168			status = "disabled";
169		};
170
171		lpuart2: uart@4006c000 {
172			compatible = "nxp,lpuart";
173			reg = <0x4006c000 0x1000>;
174			interrupts = <14 0>;
175			clocks = <&pcc 0x1b0 KINETIS_PCC_SRC_FIRC_ASYNC>;
176			status = "disabled";
177		};
178
179		lptmr0: lptmr@40040000 {
180			compatible = "nxp,lptmr";
181			reg = <0x40040000 0x1000>;
182			interrupts = <29 0>;
183			clock-frequency = <128000>;
184			prescaler = <1>;
185			clk-source = <1>;
186			resolution = <16>;
187		};
188
189		porta: pinmux@40049000 {
190			compatible = "nxp,port-pinmux";
191			reg = <0x40049000 0x1000>;
192			clocks = <&pcc 0x124 KINETIS_PCC_SRC_NONE_OR_EXT>;
193		};
194
195		portb: pinmux@4004a000 {
196			compatible = "nxp,port-pinmux";
197			reg = <0x4004a000 0x1000>;
198			clocks = <&pcc 0x128 KINETIS_PCC_SRC_NONE_OR_EXT>;
199		};
200
201		portc: pinmux@4004b000 {
202			compatible = "nxp,port-pinmux";
203			reg = <0x4004b000 0x1000>;
204			clocks = <&pcc 0x12c KINETIS_PCC_SRC_NONE_OR_EXT>;
205		};
206
207		portd: pinmux@4004c000 {
208			compatible = "nxp,port-pinmux";
209			reg = <0x4004c000 0x1000>;
210			clocks = <&pcc 0x130 KINETIS_PCC_SRC_NONE_OR_EXT>;
211		};
212
213		porte: pinmux@4004d000 {
214			compatible = "nxp,port-pinmux";
215			reg = <0x4004d000 0x1000>;
216			clocks = <&pcc 0x134 KINETIS_PCC_SRC_NONE_OR_EXT>;
217		};
218
219		pmc: pmc@4007d000 {
220			reg = <0x4007d000 0x1000>;
221
222			lpo: lpo128k {
223				compatible = "fixed-clock";
224				clock-frequency = <128000>;
225				#clock-cells = <0>;
226			};
227		};
228
229		wdog: watchdog@40052000 {
230			compatible = "nxp,wdog32";
231			reg = <0x40052000 0x1000>;
232			interrupts = <28 0>;
233			clocks = <&lpo>;
234			clk-source = <1>;
235			clk-divider = <256>;
236			status = "disabled";
237		};
238
239		gpios0: gpios0@400ff000 {
240			compatible = "nxp,gpio-cluster";
241			interrupts = <7 2>;
242			reg = <0x400ff000 0x200>;
243			ranges = <0x0 0x400ff000 0x200>;
244			#address-cells = <1>;
245			#size-cells = <1>;
246
247			gpioa: gpio@400ff000 {
248				compatible = "nxp,kinetis-gpio";
249				status = "disabled";
250				reg = <0x0 0x40>;
251				gpio-controller;
252				#gpio-cells = <2>;
253				nxp,kinetis-port = <&porta>;
254			};
255
256			gpioe: gpio@400ff100 {
257				compatible = "nxp,kinetis-gpio";
258				status = "disabled";
259				reg = <0x100 0x40>;
260				gpio-controller;
261				#gpio-cells = <2>;
262				nxp,kinetis-port = <&porte>;
263			};
264
265			fgpioa: gpio@f8000000 {
266				compatible = "nxp,kinetis-gpio";
267				status = "disabled";
268				reg = <0xf8000000 0x40>;
269				gpio-controller;
270				#gpio-cells = <2>;
271				nxp,kinetis-port = <&porta>;
272			};
273
274			fgpioe: gpio@f8000100 {
275				compatible = "nxp,kinetis-gpio";
276				status = "disabled";
277				reg = <0xf8000100 0x40>;
278				gpio-controller;
279				#gpio-cells = <2>;
280				nxp,kinetis-port = <&porte>;
281			};
282		};
283
284		gpios1: gpios1@400ff040 {
285			compatible = "nxp,gpio-cluster";
286			interrupts = <26 2>;
287			reg = <0x400ff040 0x200>;
288			ranges = <0x40 0x400ff040 0x200>;
289			#address-cells = <1>;
290			#size-cells = <1>;
291
292			gpiob: gpio@400ff040 {
293				compatible = "nxp,kinetis-gpio";
294				status = "disabled";
295				reg = <0x40 0x40>;
296				gpio-controller;
297				#gpio-cells = <2>;
298				nxp,kinetis-port = <&portb>;
299			};
300
301			gpioc: gpio@400ff080 {
302				compatible = "nxp,kinetis-gpio";
303				status = "disabled";
304				reg = <0x80 0x40>;
305				gpio-controller;
306				#gpio-cells = <2>;
307				nxp,kinetis-port = <&portc>;
308			};
309
310			gpiod: gpio@400ff0c0 {
311				compatible = "nxp,kinetis-gpio";
312				status = "disabled";
313				reg = <0xc0 0x40>;
314				gpio-controller;
315				#gpio-cells = <2>;
316				nxp,kinetis-port = <&portd>;
317			};
318
319			fgpiob: gpio@f8000040 {
320				compatible = "nxp,kinetis-gpio";
321				status = "disabled";
322				reg = <0xf8000040 0x40>;
323				gpio-controller;
324				#gpio-cells = <2>;
325				nxp,kinetis-port = <&portb>;
326			};
327
328			fgpioc: gpio@f8000080 {
329				compatible = "nxp,kinetis-gpio";
330				status = "disabled";
331				reg = <0xf8000080 0x40>;
332				gpio-controller;
333				#gpio-cells = <2>;
334				nxp,kinetis-port = <&portc>;
335			};
336
337			fgpiod: gpio@f80000c0 {
338				compatible = "nxp,kinetis-gpio";
339				status = "disabled";
340				reg = <0xf80000c0 0x40>;
341				gpio-controller;
342				#gpio-cells = <2>;
343				nxp,kinetis-port = <&portd>;
344			};
345		};
346
347		ftm0: ftm@40038000 {
348			compatible = "nxp,ftm";
349			reg = <0x40038000 0x1000>;
350			interrupts = <17 0>;
351			clocks = <&pcc 0xe0 KINETIS_PCC_SRC_FIRC_ASYNC>;
352			prescaler = <16>;
353			status = "disabled";
354		};
355
356		ftm1: ftm@40039000 {
357			compatible = "nxp,ftm";
358			reg = <0x40039000 0x1000>;
359			interrupts = <18 0>;
360			clocks = <&pcc 0xe4 KINETIS_PCC_SRC_FIRC_ASYNC>;
361			prescaler = <16>;
362			status = "disabled";
363		};
364
365		ftm2: ftm@4003a000 {
366			compatible = "nxp,ftm";
367			reg = <0x4003a000 0x1000>;
368			interrupts = <19 0>;
369			clocks = <&pcc 0xe8 KINETIS_PCC_SRC_FIRC_ASYNC>;
370			prescaler = <16>;
371			status = "disabled";
372		};
373
374		pwt: pwt@40056000 {
375			compatible = "nxp,kinetis-pwt";
376			reg = <0x40056000 0x1000>;
377			interrupts = <29 0>;
378			clocks = <&scg KINETIS_SCG_BUS_CLK>;
379			prescaler = <1>;
380			status = "disabled";
381
382			#pwm-cells = <3>;
383		};
384
385		lpi2c0: i2c@40066000 {
386			compatible = "nxp,lpi2c";
387			clock-frequency = <I2C_BITRATE_STANDARD>;
388			#address-cells = <1>;
389			#size-cells = <0>;
390			reg = <0x40066000 0x1000>;
391			interrupts = <8 0>;
392			clocks = <&pcc 0x198 KINETIS_PCC_SRC_FIRC_ASYNC>;
393			status = "disabled";
394		};
395
396		lpi2c1: i2c@40067000 {
397			compatible = "nxp,lpi2c";
398			clock-frequency = <I2C_BITRATE_STANDARD>;
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <0x40067000 0x1000>;
402			interrupts = <9 0>;
403			clocks = <&pcc 0x19c KINETIS_PCC_SRC_FIRC_ASYNC>;
404			status = "disabled";
405		};
406
407		rtc: rtc@4003d000 {
408			compatible = "nxp,rtc";
409			reg = <0x4003d000 0x1000>;
410			interrupts = <20 0>;
411			clock-frequency = <32768>;
412			prescaler = <32768>;
413			status = "disabled";
414		};
415
416		cmp0: cmp@40073000 {
417			compatible = "nxp,kinetis-acmp";
418			reg = <0x40073000 0x1000>;
419			interrupts = <16 0>;
420			clocks = <&scg KINETIS_SCG_BUS_CLK>;
421			status = "disabled";
422		};
423
424		lpspi0: spi@4002c000 {
425			compatible = "nxp,lpspi";
426			reg = <0x4002c000 0x1000>;
427			interrupts = <10 0>;
428			clocks = <&pcc 0xb0 KINETIS_PCC_SRC_FIRC_ASYNC>;
429			status = "disabled";
430			#address-cells = <1>;
431			#size-cells = <0>;
432		};
433
434		lpspi1: spi@4002d000 {
435			compatible = "nxp,lpspi";
436			reg = <0x4002d000 0x1000>;
437			interrupts = <11 0>;
438			clocks = <&pcc 0xb4 KINETIS_PCC_SRC_FIRC_ASYNC>;
439			status = "disabled";
440			#address-cells = <1>;
441			#size-cells = <0>;
442		};
443
444		edma: dma-controller@40008000 {
445			compatible = "nxp,mcux-edma";
446			nxp,version = <2>;
447			dma-channels = <8>;
448			dma-requests = <64>;
449			nxp,mem2mem;
450			reg = <0x40008000 0x1000>, <0x40021000 0x1000>;
451			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
452				     <4 0>;
453			status = "disabled";
454			#dma-cells = <2>;
455			irq-shared-offset = <4>;
456		};
457
458		flexio: flexio@4005a000 {
459			compatible = "nxp,flexio";
460			reg = <0x4005a000 0x1000>;
461			status = "disabled";
462			interrupts = <23 0>;
463			clocks = <&pcc 0x168 KINETIS_PCC_SRC_FIRC_ASYNC>;
464		};
465	};
466};
467
468&nvic {
469	arm,num-irq-priority-bits = <2>;
470};
471