Lines Matching +full:irq +full:- +full:shared +full:- +full:offset
4 * SPDX-License-Identifier: Apache-2.0
29 unsigned int irq; member
86 * @param flags Arch-specific IRQ configuration flag
103 * @param irq The IRQ we wish to trigger via MSI.
106 * @return A (32-bit) value for the MSI MAP register.
108 extern uint32_t pcie_msi_map(unsigned int irq,
117 * @param irq The IRQ we wish to trigger via MSI.
119 * @return A (16-bit) value for MSI MDR register.
121 extern uint16_t pcie_msi_mdr(unsigned int irq,
130 * @param irq The IRQ we wish to trigger via MSI.
136 unsigned int irq);
139 * @brief Check if the given PCI endpoint supports MSI/MSI-X
142 * @return true if the endpoint support MSI/MSI-X
147 * The first word of the MSI capability is shared with the
158 #define PCIE_MSI_MCR_64 0x00800000U /* 64-bit MSI */
171 * As for MSI, he first word of the MSI-X capability is shared
177 #define PCIE_MSIX_MCR_EN 0x80000000U /* Enable MSI-X */
185 #define PCIE_MSIX_TR_OFFSET 0xFFFFFFF8U /* Offset mask */
189 #define PCIE_MSIX_PBA_OFFSET 0xFFFFFFF8U /* Offset mask */
191 #define PCIE_VTBL_MA 0U /* Msg Address offset */
192 #define PCIE_VTBL_MUA 4U /* Msg Upper Address offset */
193 #define PCIE_VTBL_MD 8U /* Msg Data offset */
194 #define PCIE_VTBL_VCTRL 12U /* Vector control offset */