4  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/arch/xtensa/irq.h>
18 #include <zephyr/irq.h>
22  * architectural IRQ 4 (see below), run by a Designware interrupt
25  * (i.e. interrupts 0-31 are Xtensa IRQs, 32 represents DW input 0,
28  * That IRQ 4 indeed has an interrupt type of "EXTERN_LEVEL" and an
30  * IRQ 1 and a level 3 on IRQ 6, but nothing seems wired there.  Note
31  * that this level 2 ISR is also shared with the CCOUNT timer on IRQ3.
49  * + Drivers manage ACE_DINT themselves, as there are device-specific
51  *   core-asymmetric interrupt routing needs to happen, it happens
61 /* ACE also has per-core instantiations of a Synopsys interrupt
74 static inline bool is_dw_irq(uint32_t irq)  in is_dw_irq()  argument
76 	if (((irq & XTENSA_IRQ_NUM_MASK) == ACE_INTC_IRQ)  in is_dw_irq()
77 	    && ((irq & ~XTENSA_IRQ_NUM_MASK) != 0)) {  in is_dw_irq()
84 void dw_ace_irq_enable(const struct device *dev, uint32_t irq)  in dw_ace_irq_enable()  argument
88 	if (is_dw_irq(irq)) {  in dw_ace_irq_enable()
92 			ACE_INTC[i].irq_inten_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));  in dw_ace_irq_enable()
93 			ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));  in dw_ace_irq_enable()
95 	} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {  in dw_ace_irq_enable()
96 		xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));  in dw_ace_irq_enable()
100 void dw_ace_irq_disable(const struct device *dev, uint32_t irq)  in dw_ace_irq_disable()  argument
104 	if (is_dw_irq(irq)) {  in dw_ace_irq_disable()
108 			ACE_INTC[i].irq_inten_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));  in dw_ace_irq_disable()
109 			ACE_INTC[i].irq_intmask_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));  in dw_ace_irq_disable()
111 	} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {  in dw_ace_irq_disable()
112 		xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));  in dw_ace_irq_disable()
116 int dw_ace_irq_is_enabled(const struct device *dev, unsigned int irq)  in dw_ace_irq_is_enabled()  argument
120 	if (is_dw_irq(irq)) {  in dw_ace_irq_is_enabled()
121 		return ACE_INTC[0].irq_inten_l & BIT(ACE_IRQ_FROM_ZEPHYR(irq));  in dw_ace_irq_is_enabled()
122 	} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {  in dw_ace_irq_is_enabled()
123 		return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));  in dw_ace_irq_is_enabled()
130 int dw_ace_irq_connect_dynamic(const struct device *dev, unsigned int irq,  in dw_ace_irq_connect_dynamic()  argument
135 	/* Simple architecture means that the Zephyr irq number and  in dw_ace_irq_connect_dynamic()
141 	z_isr_install(irq, routine, parameter);  in dw_ace_irq_connect_dynamic()
142 	return irq;  in dw_ace_irq_connect_dynamic()
151 		uint32_t bit = find_lsb_set(fs) - 1;  in dwint_isr()
152 		uint32_t offset = CONFIG_2ND_LVL_ISR_TBL_OFFSET + bit;  in dwint_isr()  local
153 		struct _isr_table_entry *ent = &_sw_isr_table[offset];  in dwint_isr()
156 		ent->isr(ent->arg);  in dwint_isr()