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/Zephyr-latest/dts/bindings/i3c/
Di3c-device.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: i3c
16 For I3C devices, the 3 fields are static address, first half
17 of Provisioned ID, and the second half of the Provisioned ID.
22 2. First half of the Provisioned ID contains the manufacturer
23 ID left-shifted by 1, where the manufacturer ID is
24 the bits 33-47 (zero-based) of the 48-bit Provisioned ID.
25 3. Second half of the Provisioned ID contains the combination of
26 the part ID (bits 16-31 of the Provisioned ID) left-shifted
27 by 16, and the instance ID (bits 12-15 of the Provisioned ID)
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dnxp,imx-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
19 run-in-wait:
24 run-in-debug:
39 - "immediate"
40 - "half-cycle"
41 - "full-cycle"
42 - "half-and-full-cycle"
44 Select how to load the buffered-registers with new values:
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/Zephyr-latest/include/zephyr/net/
Dmii.h5 * SPDX-License-Identifier: Apache-2.0
33 /** Auto-Negotiation Advertisement Register */
35 /** Auto-Negotiation Link Partner Ability Reg */
37 /** Auto-Negotiation Expansion Register */
39 /** Auto-Negotiation Next Page Transmit Register */
41 /** Auto-Negotiation Link Partner Received Next Page Reg */
43 /** 1000BASE-T Control Register */
45 /** 1000BASE-T Status Register */
54 /* Basic Mode Control Register (BMCR) bit definitions */
61 /** Auto-Negotiation enable */
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Dphy.h8 * Copyright (c) 2021 IP-Logix Inc.
11 * SPDX-License-Identifier: Apache-2.0
33 /** 10Base-T Half-Duplex */
34 LINK_HALF_10BASE_T = BIT(0),
35 /** 10Base-T Full-Duplex */
36 LINK_FULL_10BASE_T = BIT(1),
37 /** 100Base-T Half-Duplex */
38 LINK_HALF_100BASE_T = BIT(2),
39 /** 100Base-T Full-Duplex */
40 LINK_FULL_100BASE_T = BIT(3),
[all …]
Dgptp.h4 * SPDX-License-Identifier: Apache-2.0
52 /** High half. */
55 /** Low half. */
63 /** High half. */
66 /** Low half. */
98 /* Pre-calculated constants */
104 /* Message types. Event messages have BIT(3) set to 0, and general messages
105 * have that bit set to 1. IEEE 802.1AS chapter 10.5.2.2.2
118 #define GPTP_IS_EVENT_MSG(msg_type) (!((msg_type) & BIT(3)))
184 /** Control value. Sync: 0, Follow-up: 2, Others: 5. */
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/Zephyr-latest/dts/bindings/dma/
Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
30 -bit 9 : Peripheral Increment Address
33 -bit 10 : Memory Increment Address
36 -bit 11-12 : Peripheral data size
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Dandestech,atcdmac300.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
33 3. channel-config: A 32bit mask specifying the DMA channel configuration
35 -bit 0-1 : Direction (see dma.h)
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Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
28 0x1: Half-word (16 bits)
31 -bit 13-14 : Memory data size
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Dst,stm32-dma-v2bis.yaml2 # SPDX-License-Identifier: Apache-2.0
11 described in the dma.txt file, using a 2-cell specifier for each
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
17 -bit 5 : DMA cyclic mode config
20 -bit 6-7 : Direction (see dma.h)
25 -bit 9 : Peripheral Increment Address
28 -bit 10 : Memory Increment Address
31 -bit 11-12 : Peripheral data size
33 0x1: STM32_DMA_PERIPH_16BITS: Half-word (16 bits)
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Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
30 0x1: Half-word (16 bits)
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Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
24 -bit 9 : Peripheral Increment Address
27 -bit 10 : Memory Increment Address
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Dst,stm32-dma-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
10 described in the dma.txt file, using a four-cell specifier for each
13 described in the dma.txt file, using a 3-cell specifier for each
15 1. channel: the dma stream from 1 to <dma-requests>
17 this value is 0 for Memory-to-memory transfers
18 or a value between <1> .. <dma-generators> (not supported yet)
19 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
20 3. channel-config: A 32bit mask specifying the DMA channel configuration
23 -bit 5 : DMA cyclic mode config
26 -bit 6-7 : Direction (see dma.h)
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/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
28 /* 10 Mbit/s transfer speed with half duplex. */
32 /* 100 Mbit/s transfer speed with half duplex. */
120 /* Port 5 Force Speed control bit */
121 #define P5_SPEED_100M ~BIT(0)
122 /* Port 5 Force Duplex control bit */
123 #define P5_FULL_DUPLEX ~BIT(1)
124 /* Port 5 Force Link control bit. Only available in force mode. */
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/Zephyr-latest/dts/bindings/wifi/
Dinfineon,airoc-wifi-spi.yaml2 AIROC Wi-Fi Connectivity over SPI.
4 compatible: "infineon,airoc-wifi"
6 include: [spi-device.yaml, "infineon,airoc-wifi.yaml"]
9 wifi-host-wake-gpios:
12 bus-select-gpios:
16 wifi-reg-on-gpios goes high to select SPI bus mode.
17 type: phandle-array
19 spi-half-duplex:
21 Use half-duplex communication; if not present, full-
25 spi-word-size:
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/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dcpu_init.h2 * SPDX-License-Identifier: Apache-2.0
9 #include <xtensa/config/core-isa.h>
16 #define ATOMCTL_BY_RCW BIT(0) /* RCW Transaction for Bypass Memory */
17 #define ATOMCTL_WT_RCW BIT(2) /* RCW Transaction for Writethrough Cacheable Memory */
18 #define ATOMCTL_WB_RCW BIT(4) /* RCW Transaction for Writeback Cacheable Memory */
21 /* Low-level CPU initialization. Call this immediately after entering
30 /* First, we need to power the cache SRAM banks on! Write a bit in cpu_early_init()
31 * for each cache way in the bottom half of the L1CCFG register in cpu_early_init()
32 * and poll the top half for them to turn on. in cpu_early_init()
34 uint32_t dmask = BIT(ADSP_CxL1CCAP_DCMWC) - 1; in cpu_early_init()
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/Zephyr-latest/arch/xtensa/core/
Dxtensa_intgen.py5 # Pass an Xtensa core-isa.h file on stdin or the command line, emits a
8 # FIXME: looking at the assembly generated by the ESP-32 toolchain,
31 cindent -= 1
44 cprint("if (mask & BIT(%d)) {" % i)
45 cprint("mask = BIT(%d);" % i)
50 half = int(len(ints)/2)
53 for i in ints[0:half]:
56 emit_int_handler(ints[0:half])
58 emit_int_handler(ints[half:])
63 # Annoyingly need to join lines and remove #-marked annotations. Some
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/Zephyr-latest/drivers/ethernet/
Deth_adin2111_priv.h4 * SPDX-License-Identifier: Apache-2.0
28 #define ADIN2111_RESET_SWRESET BIT(0)
33 #define ADIN2111_CONFIG0_SYNC BIT(15)
35 #define ADIN2111_CONFIG0_TXFCSVE BIT(14)
37 #define ADIN2111_CONFIG0_ZARFE BIT(12)
39 #define ADIN2111_CONFIG0_CSARFE BIT(13)
41 #define ADIN2111_CONFIG0_TXCTE BIT(9)
43 #define ADIN2111_CONFIG0_RXCTE BIT(8)
48 #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14)
50 #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13)
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Dphy_xlnx_gem.c6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
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/Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_shi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
32 #define HAL_INSTANCE(dev) (struct shi_reg *)(((const struct shi_npcx_config *)(dev)->config)->base)
40 /* Half output buffer size */
42 /* Half input buffer size */
48 * This affects the slowest SPI clock we can support. A delay of 8192 us permits a 512-byte request
62 * Space allocation of the past-end status byte (EC_SHI_PAST_END) in the out_msg buffer.
73 * one last past-end byte at the end so any additional bytes clocked out by
81 * overhead, as passed to the host command handler, must be 32-bit aligned.
87 SHI_STATE_NONE = -1,
117 /* Chip-select interrupts */
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/Zephyr-latest/arch/arc/
DCMakeLists.txt1 # SPDX-License-Identifier: Apache-2.0
6 zephyr_cc_option(-g3 -gdwarf-2)
11 zephyr_cc_option(-fno-delete-null-pointer-checks)
13 zephyr_cc_option_ifdef(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS -munaligned-access)
18 # For ARCv2 the default register is usually not specified - so we need to specify it
20 zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mtp-regno=26)
22 # If thread local storage isn't used - we can safely schedule thread pointer register
23 zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mtp-regno=none)
33 zephyr_compile_options(-Ml)
34 # Instruct MWDT assembler not to warn when we load only lower half (32bit) of symbol
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/Zephyr-latest/modules/cmsis-dsp/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
8 bool "CMSIS-DSP Library Support"
10 This option enables the CMSIS-DSP library.
44 * Complex-by-Complex Multiplication
45 * Complex-by-Real Multiplication
62 * Sine-Cosine
75 * Fixed-Point Division
92 * Levinson-Durbin Algorithm
167 * Kullback-Leibler Divergence
176 * Vector 8-bit Integer Value Conversion
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/Zephyr-latest/dts/bindings/mipi-dbi/
Dzephyr,mipi-dbi-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 MIPI-DBI Mode C compatible SPI controller. This driver emulates MIPI DBI
7 compatible: "zephyr,mipi-dbi-spi"
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
12 spi-dev:
19 dc-gpios:
20 type: phandle-array
25 reset-gpios:
26 type: phandle-array
30 xfr-min-bits:
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/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
26 This information includes the aggregated GIRQ number, GIRQ bit
28 connection of the GIRQ bit.
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
42 Defaults to 1 for full duplex driver's support for full-duplex spi.
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/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
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/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,ra-sdram.yaml2 # SPDX-License-Identifier: Apache-2.0
7 pinctrl-0 = <&sdram_default>;
8 pinctrl-names = "default";
10 auto-refresh-interval = <10>;
11 auto-refresh-count = <8>;
12 precharge-cycle-count = <3>;
13 multiplex-addr-shift = "10-bit";
14 edian-mode = "little-endian";
15 continuous-access;
16 bus-width = "16-bit";
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